Jeehwan Kim

Peripheral arterial disease (PAD) is commonly treated with stent implantation, but long-term durability is limited by cyclic deformation in the lower limbs, leading to fracture or restenosis. We present a novel wireless surface acoustic wave (SAW)-based strain sensor integrated into arterial stents, enabling real-time monitoring of stent deformation. To evaluate feasibility, we developed a non-metallic bending test platform simulating physiologic motion and pulsatile flow. Preliminary data demonstrate that the SAW sensor reliably detects strain with strong correlation to imposed bending curvature, and that the test platform allows reproducible assessment under controlled conditions. This work establishes a foundation for next-generation smart stents with continuous biomechanical monitoring.

Ferroelectric capacitive memory (FeCAP) holds enormous potential for low-power, high-density in-memory computing. While hafnia-based FeCAPs have attracted attention for their silicon compatibility, they suffer from limited performance, such as a narrow memory window and relatively high switching fields. In this work, an FeCAP device is developed on the basis of a single-crystalline barium titanate (BTO) membrane, a perovskite oxide thin film that can be epitaxially lifted off and transferred onto a silicon platform. By engineering the device structure and epitaxy process, polarization asymmetry is introduced in capacitance-voltage characteristics. The resulting BTO-based FeCAP exhibits superior memory behavior, including a wide memory window of 308 picofarads and a low switching field of 0.005 megavolts per centimeter, outperforming conventional hafnia-based FeCAPs. Furthermore, these properties are preserved after active layer transfer onto a silicon platform. This approach provides a viable pathway for high-quality BTO to integrate into industry-compatible processes and to drive progress in future logic/memory applications.

Displays are one of the most indispensable electronic devices used in our daily lives. Over the past decades, display technology has evolved relentlessly, driven by innovation in materials, structures, and manufacturing processes that have enabled higher image quality, larger screen size, slimmer form factor, and novel functionalities. The display market is currently dominated by liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, but significant investment and research efforts are being directed toward emerging self-emissive display technologies, such as micro-light-emitting diodes (micro-LEDs), as well as unconventional applications such as transparent, deformable, and near-eye displays. This review article begins with a historical background of self-emissive display technology and an overview of the recent advances in organic-, quantum dot-, perovskite-, and micro-LED displays. We then critically review the current state of micro-LED technology, including its size-dependent performance issues, different types of mass transfer technologies, backplane interconnection techniques, methods for detection/repair of defective pixels, and emerging display applications, including transparent, deformable, and virtual and augmented reality (VR/AR) displays.

Artificial Optoelectronic Synapse In article number 2418582, Jin-Hong Park, Saeroonter Oh, and co-workers present an artificial optoelectronic synapse capable of bidirectional post-synaptic current modulation. This innovative design eliminates the need for differential synapse pairs while supporting essential synaptic functions. A fabricated synapse array experimentally demonstrates compatibility with multiply-accumulate (MAC) operations, and simulations using the MNIST dataset underscore the energy efficiency of the proposed neuromorphic system.

We experimentally demonstrate a single photon source in L-band using polarization-maintaining fluoride fiber. Using a 1310-nm CW laser beam single photons were successfully generated at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.57 \mu ~\mathrm{m}$</tex> on the basis of spontaneous four-wave mixing.

Abstract Conventional hardware neural networks (HW‐NNs) have relied on unidirectional current flow of artificial synapses, necessitating a differential pair of the synapses for weight core implementation. Here, an artificial optoelectronic synapse capable of bidirectional post‐synaptic current ( I PSC ) is presented, eliminating the need for differential synapse pairs. This is achieved through an asymmetric metal contact structure that induces a built‐in electric field for directional flow of photogenerated carriers, and a charge trapping/de‐trapping layer in the gate stack ( h ‐BN/weight control layer) that can modulate the surface potential of the semiconductor channel (WSe 2 ) using electrical signals. This structure enables precise control over the direction and magnitude of injected charge. The device demonstrates key synaptic behaviors, such as long‐term potentiation/depression and spike‐timing‐dependent plasticity. A fabricated 3 × 2 artificial synapse array shows that the bidirectional I PSC characteristic is compatible with multiply‐accumulate operations. Finally, the feasibility of these synapses in HW‐NNs is demonstrated through training and inference simulations using the MNIST handwritten digits dataset, yielding competitive recognition rates and reduced total energy consumption for updating weights of the weight core compared to unidirectional I PSC ‐based systems. This approach paves the way toward more compact and energy‐efficient brain‐inspired computing systems.

Abstract This research explores the feasibility of using the photothermal effect in TiO 2 microparticles (MPs) to measure mid-infrared (MIR) laser output power, introducing a new application of the photothermal effect in MPs. The MIR power measurement setup is based on an optical fiber-based Fabry-Pérot interferometer (FPI) structure, which includes a silica fiber ferrule, a polymer layer, a TiO 2 MP layer, and a ZBLAN fiber ferrule. The power of a 1550 nm probe beam in reflection mode of the FPI configuration was found to change linearly with 2.7 μ m laser output power due to the photothermal conversion effect in the TiO 2 MPs. The MIR laser output power was indirectly measured by detecting changes in the reflected 1550 nm probe beam power with a low-cost 1.5 μ m InGaAs/InP-based optical power meter. This setup could measure MIR optical power in a range from 0 to 2 mW.

The quality of the metal contact of devices can be significantly improved through high-temperature annealing, which enhances the crystal structure and reduces contamination. However, high-temperature annealing can adversely deteriorate the metal/semiconductor interface, resulting in the oxidation of the metal by the interdiffusion of oxygen atoms. Here, we explored the oxidation of the tungsten (W) contact interface on the β-Ga 2 O 3 epitaxial layer after high-temperature annealing, causing the electrical instability of W/β-Ga 2 O 3 Schottky barrier diodes (SBDs). To address the challenge posed by the trade-off between the improvement of the tungsten’s crystalline structure and the oxidation of the tungsten surface after annealing, we proposed to exfoliate and transfer graphene to β-Ga 2 O 3 utilizing a layer-resolved graphene transfer (LRGT) technique as an oxygen diffusion barrier for the surface of β-Ga 2 O 3 . The insertion of a graphene monolayer has exhibited a clean and abrupt W/β-Ga 2 O 3 interface without oxygen intermixing. This resulted in a stable leakage current for β-Ga 2 O 3 SBD, approximately 4.34 × 10 –5 A/cm 2, 2.97 × 10 –5 A/cm 2, and 2.55 × 10 –5 A/cm 2 for as-deposited, 400 °C-annealed, and 600 °C-annealed devices, respectively. Additionally, a consistent Schottky barrier height of approximately 0.80 eV and an ideality factor of 2 were maintained across all devices. Notably, the breakdown voltage remained stable at approximately −200 V, which is relatively low compared to other reported β-Ga 2 O 3 devices. However, the key achievement of our work is the minimal dependence of the device’s performance on annealing temperature, a result directly attributed to the incorporation of the graphene monolayer. This highlights the primary objective of using graphene: to enhance the thermal stability of β-Ga 2 O 3 -based devices, facilitating more reliable performance in high-temperature environments. Furthermore, the insertion of a graphene monolayer resulted in heightened thermal stability, allowing devices to operate reliably up to a temperature of 150 °C, with stable Schottky barrier height and ideality factor in stark contrast to their counterparts without the graphene Schottky barrier diode. Utilizing SILVACO TCAD simulations, we observed a crucial role played by the graphene monolayer in significantly improving heat dissipation in β-Ga 2 O 3 Schottky barrier diodes. These unchanging device parameters, subsequent to the insertion of a graphene monolayer, provide a compelling explanation for the role of the graphene monolayer as an effective diffusion barrier material for β-Ga 2 O 3 for improving its application in high-power devices.

Freestanding semiconductor membranes hold significant potential for heterogeneous integration technology and flexible electronics. Remote epitaxy, which leverages electrostatic interactions between epilayers and substrates through two-dimensional (2D) materials such as graphene, offers a promising solution for fabricating freestanding single-crystal membranes. Although the thinness, uniformity, and cleanness of 2D materials need to be meticulously controlled to enable the remote epitaxy of high-quality thin films, attaining such ideal growth templates has been challenging thus far. In this study, we demonstrate a controlled graphitization method to form a pristine graphene buffer layer (GBL) directly on SiC substrates and utilize this GBL template for GaN remote epitaxy. The quasi-two-dimensional GBL layer obtained by the method is completely free of damage or contamination, facilitating strong epitaxial interaction between the GaN epilayer and the SiC substrate. Furthermore, we reveal that a two-step growth of GaN on this GBL template enables the formation of single-crystal GaN epilayers and their exfoliation. Thus, this study represents an important step toward developing high-quality, freestanding semiconductor membranes.

The advancement in semiconductor technology through the integration of more devices on a chip has reached a point where device scaling alone is no longer an efficient way to improve the device performance. One issue lies in the interconnects connecting the transistors, in which the resistivity of metals increases exponentially as their dimensions are scaled down to match those of the transistors. As a result, the total signal processing delay is dominated by the resistance-capacitance (RC) delay from the interconnects rather than the delay from the transistors' switching speed. This bottleneck has spurred efforts both in academia and industry to explore alternative materials and disruptive device structures. Therefore, we suggest strategies to overcome the RC delay of the interconnects in both material and device aspects.

Continuing miniaturization of devices has reached its limits as a means to boost the performance of cutting-edge electronic products. Instead, 3D heterogeneous integration, which involves vertically stacking wafers with embedded electronic devices, is emerging as the leading approach for augmenting performance. This method, however, demands complex procedures including: creating through-silicon vias (TSVs), filling these vias with copper, and bonding the wafers via micro-bumps or Cu hybrid bonding. Eliminating the use of wafers in this complex 3D assembly could streamline the process and reduce the length of data paths. Yet, current technologies scarcely allow for the removal and reassembly of active single-crystalline devices from wafers. Moreover, directly depositing device layers onto existing circuits presents additional hurdles. Over the last decade, we have pioneered techniques for transferring single-crystalline semiconductor device membranes, significantly advancing 3D heterogeneous integration [1-8]. More recently, we have achieved a breakthrough in monolithically growing pristine single-crystalline 2D semiconductors on non-crystalline insulators at a BEOL compatible temperature, pushing the boundaries of monolithic 3D heterointegration even further [9]. In my presentation, I will explore our unprecedented 3D integration methods and their implications for state-of-the-art electronics [9, 10], optoelectronics [11], and bioelectronics [12-13]. References : [1] Nature 544, 340 (2017), [2] Nature Materials 17, 999 (2018), [3] Nature Materials 18, 550 (2019), [4] Nature Nanotechnology 15, 272-276 (2020), [5] Nature Electronics , 2, 439 (2019), [6] Nature , 578, 75 (2020), [7] Nature Nanotechnology 15, 574 (2020), [8] Nature Nanotechnology , 17, 1054 (2022), [9] Nature , 614, 88 (2023), [10] Nature Electronics , 5, 386 (2022), [11] Nature , 614, 81 (2023), [12] Science Advances , 7, 27 (2021) [13] Science 377, 859 (2022)

Remote epitaxy is taking center stage in creating freestanding complex oxide thin films with high crystallinity that could serve as an ideal building block for stacking artificial heterostructures with distinctive functionalities. However, there exist technical challenges, particularly in the remote epitaxy of perovskite oxides associated with their harsh growth environments, making the graphene interlayer difficult to survive. Transferred graphene, typically used for creating a remote epitaxy template, poses limitations in ensuring the yield of perovskite films, especially when pulsed laser deposition (PLD) growth is carried out, since graphene degradation can be easily observed. Here, we employ spectroscopic ellipsometry to determine the critical factors that damage the integrity of graphene during PLD by tracking the change in optical properties of graphene in situ . To mitigate the issues observed in the PLD process, we propose an alternative growth strategy based on molecular beam epitaxy to produce single-crystalline perovskite membranes.

Two-dimensional (2D) materials have garnered significant attention due to their exceptional properties requisite for next-generation electronics, including ultrahigh carrier mobility, superior mechanical flexibility, and unusual optical characteristics. Despite their great potential, one of the major technical difficulties toward lab-to-fab transition exists in the seamless integration of 2D materials with classic material systems, typically composed of three-dimensional (3D) materials. Owing to the self-passivated nature of 2D surfaces, it is particularly challenging to achieve well-defined interfaces when forming 3D materials on 2D materials (3D-on-2D) heterostructures. Here, we comprehensively review recent progress in 3D-on-2D incorporation strategies, ranging from direct-growth- to layer-transfer-based approaches and from non-epitaxial to epitaxial integration methods. Their technological advances and obstacles are rigorously discussed to explore optimal, yet viable, integration strategies of 3D-on-2D heterostructures. We conclude with an outlook on mixed-dimensional integration processes, identifying key challenges in state-of-the-art technology and suggesting potential opportunities for future innovation.

Abstract Bioelectronic implantable devices are adept at facilitating continuous monitoring of health and enabling the early detection of diseases, offering insights into the physiological conditions of various bodily organs. Furthermore, these advanced systems have therapeutic capabilities in neuromodulation, demonstrating their efficacy in addressing diverse medical conditions through the precise delivery of stimuli directly to specific targets. This comprehensive review explores developments and applications of bioelectronic devices within the biomedical field. Special emphasis is placed on the evolution of closed‐loop systems, which stand out for their dynamic treatment adjustments based on real‐time physiological feedback. The integration of Artificial Intelligence (AI) and edge computing technologies is discussed, which significantly bolster the diagnostic and therapeutic functions of these devices. By addressing elemental analyses, current challenges, and future directions in implantable devices, the review aims to guide the pathway for advances in bioelectronic devices.

A passively Q-switched, erbium ZBLAN fiber laser based on a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf>C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> MXene saturable absorption mirror, is experimentally demonstrated at 2.7 μm. Optical pulses with a 821 μJ energy was achieved at a 2.2-W pump power.

Two-dimensional semiconductors are an attractive material for making thin-film transistors due to their scalability, transferability, atomic thickness and relatively high carrier mobility. There is, however, a gap in performance between single-device demonstrations, which typically use single-crystalline two-dimensional films, and devices that can be integrated on a large scale using industrial methods. Here we report the 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide (MoS2) field-effect transistors. Our processes are compatible with industry, with processing performed in a commercial 200 mm fabrication facility with a yield of over 99.9%. We find that the metal–semiconductor junction in polycrystalline MoS2 is fundamentally different from its single-crystalline counterpart, and therefore, we redesign the process flow to nearly eliminate the Schottky barrier height at the metal–MoS2 contact. The resulting MoS2 field-effect transistors exhibit mobilities of 21 cm2 V−1 s−1, contact resistances of 3.8 kΩ µm and on-current densities of 120 µA µm−1, which are similar to those achieved with single-crystalline flakes. A method for integrating polycrystalline molybdenum disulfide using processes in a 200 mm fab facility can create transistors with high robustness and performance comparable with single-crystalline devices.

Electrostatic capacitors are foundational components of advanced electronics and high-power electrical systems owing to their ultrafast charging-discharging capability. Ferroelectric materials offer high maximum polarization, but high remnant polarization has hindered their effective deployment in energy storage applications. Previous methodologies have encountered problems because of the deteriorated crystallinity of the ferroelectric materials. We introduce an approach to control the relaxation time using two-dimensional (2D) materials while minimizing energy loss by using 2D/3D/2D heterostructures and preserving the crystallinity of ferroelectric 3D materials. Using this approach, we were able to achieve an energy density of 191.7 joules per cubic centimeter with an efficiency greater than 90%. This precise control over relaxation time holds promise for a wide array of applications and has the potential to accelerate the development of highly efficient energy storage systems.

Abstract An experimental and theoretical investigation into a core-pumped Dy 3+ -doped ZBLAN fiber laser with 1.1 μ m pumping was conducted to figure out a configuration for better slope efficiency. First, the laser was experimentally constructed with a simple Fabry–Pérot cavity incorporating AlF 3 no-core fiber endcaps. The maximum output power of 607 mW was obtained readily with a slope efficiency of 25%. Next, a 5-energy level model was adopted for a numerical simulation to figure out the optimum output mirror reflectivity for the particular experimental laser setup in terms of slope efficiency. The best slope efficiency of 30% was shown to be obtainable with an output mirror of a 22% reflection.

Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology.

Advanced heterogeneous integration technologies are pivotal for next-generation electronics. Single-crystalline materials are one of the key building blocks for heterogeneous integration, although it is challenging to produce and integrate these materials. Remote epitaxy is recently introduced as a solution for growing single-crystalline thin films that can be exfoliated from host wafers and then transferred onto foreign platforms. This technology has quickly gained attention, as it can be applied to a wide variety of materials and can realize new functionalities and novel application platforms. Nevertheless, remote epitaxy is a delicate process, and thus, successful execution of remote epitaxy is often challenging. Here, we elucidate the mechanisms of remote epitaxy, summarize recent breakthroughs, and discuss the challenges and solutions in the remote epitaxy of various material systems. We also provide a vision for the future of remote epitaxy for studying fundamental materials science, as well as for functional applications.

Abstract Heterogeneous integration of dissimilar crystalline materials has recently attracted considerable attention due to its potential for high-performance multifunctional electronic and photonic devices. The conventional method for fabricating heterostructures is by heteroepitaxy, in which epitaxy is performed on crystallographically different materials. However, epitaxial limitations in monolithic growth of dissimilar materials prevent implementation of high quality heterostructures, such as complex-oxides on conventional semiconductor platforms (Si, III-V and III-N). In this work, we demonstrate gallium nitride (GaN) high-electron-mobility transistors with crystalline complex-oxide material enabled by heterogeneous integration through epitaxial lift-off and direct stacking. We successfully integrate high-κ complex-oxide SrTiO 3 in freestanding membrane form with GaN heterostructure via a simple transfer process as the gate oxide. The fabricated device shows steep subthreshold swing close to the Boltzmann limit, along with negligible hysteresis and low dynamic on-resistance, indicating very low defect density between the SrTiO 3 gate oxide and GaN heterostructure. Our results show that heterogeneous integration through direct material stacking is a promising route towards fabricating functional heterostructures not possible by conventional epitaxy.

The goal of this project is to develop low-cost, high throughput and high efficiency GaAs photovoltaics (PV) by leveraging a combination of revolutionary manufacturing methods termed "remote epitaxy" and "Two-dimensional layer transfer (2DLT)" process with Dynamic-hydride vapor phase epitaxy (D-HVPE).Remote epitaxy enables the growth of defect-free single-crystalline films by copying the crystalline information from the substrate through graphene.Weak graphene-film bonding can allow fast, precise mechanical separation of the films from the graphene surface, thus permitting infinite reuse of the expensive substrate without expensive re-processing of wafer surface to produce semiconductor films [1][2][3].2DLT has proven its potential to overcome technical shortcomings of a very slow epitaxial lift technique, where etching of AlAs interlayer leaves damage on the wafer and handling of release layers occurs in chemical solution, because of the following reasons: 1) precise mechanical release from graphene does not damage the substrate (Ra < 1 nm), which can maximize reusability of substrates as post-release CMP treatment is not required, 2) fast mechanical release allows high throughput production of wafer-scale PV layers, and 3) Dry release using mechanically stable Ni metal handler allows further facile module integration.Together with the cost effective/high-throughput 2DLT, D-HVPE technique can enable high throughput epitaxy at low-cost due to high utilization rate and inexpensive precursors to produce large scale PV cells with an extreme growth rate at around 100 m/h without degrading the solar cell performance.Therefore, the approach proposed in this project can alleviate the two biggest cost barriers associated with GaAs solar cells, which are the cost of epitaxial growth and the substrate.Through this program the team aims to demonstrate the fabrication of both GaAs based solar cell with a power conversion efficiency (PCE) over 20% at a growth rate >60 m/hr while the single parent wafer is reused multiple times.Successful implementation of the proposed project will unlock a practical pathway to make the high efficiency and high throughput PVs viable in very large markets where Si is not practical including space, weight constrained and building integrated applications where flexibility or high specific weight/power are attractive. Significant Accomplishments and Conclusions:One of the most important outcomes of this project was that the team developed a method to directly grow graphene layer in wafer-scale on III-V substrates.Conventionally, graphene had to be transferred for remote epitaxy, which has imposed significant challenges in scalability, film quality, and substrate recycling, due to the transfer-related issues.The newly developed method of directly forming 2D layers by Metal-Organic Chemical Vapor Deposition (MOCVD) has realized wafer-scale, defectfree graphene formation for remote epitaxy, which has huge implications not only for solar cells but also in expanding the scalability and the possibility for heterointegration with dissimilar material platforms.Another important outcome was on better understanding of remote epitaxy mechanism.The growth of III-V on graphene is vastly different from directly growing films on III-V substrates, because the surface energy of graphene is very small, meaning that the nucleation density on graphene will be much lower than exposed III-V surfaces.Also, the graphene and the interface properties critically affect remote interaction through graphene.With this obtained knowledge regarding III-V remote epitaxy, we were able to achieve wafer-scale single-crystalline remote epitaxy, 100% exfoliation of the remote epitaxial films, as well as multiple times of GaAs wafer reusability demonstration.The general rule of thumbs found during this project will be a stepping stone for the growth and fabrication of various high-performance devices by remote epitaxy.Lastly, because remote epitaxy and 2DLT offer a pathway to isolate single-crystal membranes from the host wafers, the wafer-scale remote epitaxy processes developed in this project could open up pathways for new functionality and multi-functionality by heterointegration of remote epitaxially formed membranes.

The demand for the three-dimensional (3D) integration of electronic components is on a steady rise. The through-silicon-via (TSV) technique emerges as the only viable method for integrating single-crystalline device components in a 3D format, despite encountering significant processing challenges. While monolithic 3D (M3D) integration schemes show promise, the seamless connection of single-crystalline semiconductors without intervening wafers has yet to be demonstrated. This challenge arises from the inherent difficulty of growing single crystals on amorphous or polycrystalline surfaces post the back-end-of-the-line process at low temperatures to preserve the underlying circuitry. Consequently, a practical growth-based solution for M3D of single crystals remains elusive. Here, we present a method for growing single-crystalline channel materials, specifically composed of transition metal dichalcogenides, on amorphous and polycrystalline surfaces at temperatures lower than 400 °C. Building on this developed technique, we demonstrate the seamless monolithic integration of vertical single-crystalline logic transistor arrays. This accomplishment leads to the development of unprecedented vertical CMOS arrays, thereby constructing vertical inverters. Ultimately, this achievement sets the stage to pave the way for M3D integration of various electronic and optoelectronic hardware in the form of single crystals.

We couple halide vapor phase epitaxy (HVPE) growth of III-V materials with liftoff from an ultrathin carbon release layer to address two significant cost components in III-V device - epitaxial growth and substrate reusability. We investigate nucleation and growth of GaAs layers by HVPE on a thin amorphous carbon layer that can be mechanically exfoliated, leaving the substrate available for reuse. We study nucleation as a function of carbon layer thickness and growth rate and find island-like nucleation. We then study various GaAs growth conditions, including V/III ratio, growth temperature, and growth rate in an effort to minimize film roughness. High growth rates and thicker films lead to drastically smoother surfaces with reduced threading dislocation density. Finally, we grow an initial photovoltaic device on a carbon release layer that has an efficiency of 7.2%. The findings of this work show that HVPE growth is compatible with a carbon release layer and presents a path toward lowering the cost of photovoltaics with high throughput growth and substrate reuse.