Anantha P. Chandrakasan

) integrates around fragile wirebonds, reduces inter-element crosstalk by ~4.5 dB throughout the array, and improves axial and lateral/elevational resolutions by ~200 µm and ~70 µm, respectively. Layered Aberration-Correction Reconstruction (LACR), an adaptive 3D beamformer, compensates for heterogeneous speed-of-sound (SoS) in the breast, reducing depth localization error by 2 mm and aberration defocusing by 70 µm on average at a 5 cm depth. Nine of the ten participants in an in vitro study showed improved microtarget detection efficiency with 3D PURE relative to a conventional 2D system (p = 0.0215), analogous to detection of microcalcifications. These results, combined with in vivo imaging validation of various phenotypes, highlight the potential of 3D PURE for reliable breast imaging. Furthermore, a vision-guided computer interface, MyFUS, ensures self-guided, user-friendly, and operator-independent probe positioning for longitudinal monitoring.

Abstract Ingestible electronic systems offer a minimally invasive means to continuously monitor core body temperature, providing critical insights into a range of health conditions. However, the size of ingestible sensors often limits their use, particularly in paediatric populations. Here we report a miniaturized ingestible temperature sensor for continuous internal monitoring. The device integrates a 1 mm × 1 mm low-power (10 nW) integrated circuit, a 5 mm × 5 mm antenna for wireless backscatter communication and a coin-cell battery. The fully encapsulated system measures just 6 mm in diameter and 4 mm in height, dimensions aligned with those of US Food and Drug Administration-approved osmotic controlled-release oral delivery system and smaller than video capsule endoscopy devices, thus minimizing the risk of gastrointestinal retention. We evaluate the sensor in swine models under diverse physiological and pathophysiological conditions. This includes use in ambulatory multi-day monitoring, scenarios with inflammation-induced altered gastrointestinal transit and deployment alongside intravascular devices for vascular navigation and guidance.

ABSTRACT Effective resource‐constrained volumetric ultrasound imaging requires compact, low‐power systems capable of wide‐angle real‐time 3D imaging to accommodate small changes in placement by the operator. However, obtaining such images requires an excessive O(N 2 ) channel count, bulky electronics, and high power consumption. We introduce an end‐to‐end system architecture to enable high‐resolution, real‐time 3D ultrasound imaging in a portable form factor. We present: a convolutional optimally distributed array (CODA) geometry that drastically reduces the number of elements (from 1024 to 128), a novel chirped data acquisition (cDAQ) architecture that enhances imaging depth while operating with a 25.3 dB lower transmit amplitude than a pulsed system, and an associated new signal processing methodology. We experimentally demonstrate our system's ability to perform deep (> 11 cm), high axial resolution (< 600 µm), and wide‐angle (57°) imaging, while simultaneously reducing power consumption (29.6x reduction) and drive voltage (18 V). We validated our system in vitro and further performed in vivo human trials, demonstrating the ability to detect both tumors and cysts in breast tissue. This new architectural approach will unlock a new class of medical devices with enhanced diagnostic and long‐term monitoring capabilities and open up future wearable designs of real‐time 3D ultrasound systems.

Security vulnerabilities in deep neural network (DNN) accelerators pose risks for high-stakes applications, with off-chip memory attacks representing a critical threat to both data confidentiality and integrity. While general-purpose processors employ comprehensive cryptographic authenticated encryption for memory security, domain-specific DNN accelerators lack adequate protection, particularly against integrity violations. To address this research gap, we present Sorbet, a DNN accelerator equipped with authenticated encryption to defend against both confidentiality and integrity attacks on off-chip memory. Integrity verification introduces complex memory access patterns in DNN accelerators, as the granularity of authentication operations often clashes with the tiling strategies used for efficient off-chip memory access. Our approach tackles this challenge with a secure memory interface (SMI) module that efficiently: 1) translates the accelerator’s tile request to the required data for cryptographic authentication and 2) aligns fetched data with the memory map of the accelerator’s on-chip buffers. Moreover, our design mitigates the area and performance overhead of cryptographic operations by adopting a lightweight cipher while maintaining security requirements against splicing and replay attacks. Our fabricated chip achieves 22% latency overhead across diverse workloads, including convolutions and multihead attentions (MHAs), which can be further reduced with larger on-chip buffer size and double-buffering. It incurs only 7.9% area and 18.3% energy overhead, which is competitive with recent DNN accelerator defenses with weaker off-chip memory protection.

This article presents a processor for the acceleration of generative AI (GenAI) based on a novel heterogeneous core architecture called MEGA.mini. The processor introduces three algorithmic features: 1) fixed-point (FXP) and floating-point (FP) hybrid input activation (IA) representation; 2) a delayed-statistics-based normalization (NORM); and 3) conditional polynomial-based nonlinear activation (NLA) approximation. These features are implemented in the MEGA.mini core along with the unified tensor streaming core (UTSC). The MEGA.mini core further enhances energy efficiency through: 1) a sign-magnitude (SM)-based asynchronous dual accumulation register; 2) a dynamic FP (DFP) MAC unit; and 3) a cross-shaped memory architecture (CMA). To maintain high core utilization, three hierarchical solutions are adopted: 1) integer length update; 2) task-preloading; and 3) output synchronizer. Additionally, the UTSC minimizes hardware overhead by sharing required processing elements (PEs) of NORM and NLA, while improving accuracy through a recovery mechanism and standard-deviation-aware hyperparameter selection. Fabricated in a 28-nm process, the proposed processor achieves up to 2.05 TOPS of throughput and 64.2-TOPS/W of energy efficiency in various GenAI tasks, including both non-diffusion and diffusion models (DMs).

Autonomous and real-time medical image segmentation can analyze a large amount of imaging data that would otherwise overwhelm medical professionals. It enables critical applications including urinary retention diagnosis, neuromodulation, cardiovascular monitoring, and prenatal fetal biometry. While U-net achieves the state-of-the-art performance for biomedical applications, its skip connections and numerous layers pose compute and memory challenges for wearable devices. Existing devices rely on cloud processing, limiting deployment and raising privacy concerns. This paper presents the first fully-integrated medical image segmentation processor addressing these challenges through: 1) binary convolution datapaths with unique 4bit skip connection datapaths preserving diagnostic accuracy; 2) an interleaved memory format, halo reuse, and optimized dataflows for energy-efficient battery-powered operation; and 3) skip connection fusion and compression that reduce peak memory usage by $3.16 x$ and $1.38 x$, respectively. The $28 n m$ processor achieves 13.4 frames per second (fps) at $23 \mu \mathrm{~J}$ per frame for clinical bladder segmentation, enabling privacy-preserving continuous monitoring in emerging wearable ultrasound patches.

A novel ultrasound-transmission-based thermometry method is proposed for non-invasive deep tissue temperature monitoring. This approach estimates temperature by measuring variations in the time-of-flight (ToF) of received ultrasound waves, which are influenced by the temperature-dependent speed of sound in biological tissues. Although initially demonstrated in a single-layer model, the method is extendable to multi-layer tissue structures to measure the internal temperature of each layer. Compared to existing thermometry techniques, the proposed method provides direct, quantitative, and layer-specific temperature estimation. A human-mimicking tissue phantom was developed to experimentally validate the approach, achieving a mean error of 0.53°C, thereby demonstrating the feasibility and strong potential of ultrasound-transmission-based thermometry for accurate deep tissue temperature assessment.

• NPU with a Novel big.LITTLECore Architecture to Balance 3 Key Aspects of AI Acceleration–Efficiency: > 95% computations w/ Low-precision FXP–Performance: 3 hierarchical solutions @ MEGA+mini–Intelligence: Hybrid IA (FP for < 5% outlier data)

We present an ML-driven framework for predicting circuit performance metrics, bridging the gap between schematic and layout simulations, multi-process corner analysis, and measured silicon data. We demonstrate this using 14nm and 5nm FinFET-based ring oscillators, by collecting data across varying supply voltages, temperatures, and process corners. Using three baseline ML models—XGBoost, Random Forest, and a Neural Network—we simulate real-world design scenarios where parameter fine-tuning may not always be feasible. Key tasks include predicting layout performance from schematic data, performance prediction across process corners, and fabricated chip performance. Our results show that these models can achieve less than 5% mean absolute percentage error (MAPE) for power and frequency prediction while reducing required simulations by more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $</tex-math> </inline-formula>. When migrating from 14nm to 5nm, XGBoost and Neural Network achieve high accuracy (>0.99 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R^{2}$</tex-math> </inline-formula>) using just 10% of the otherwise required 5nm simulations. We also present an extensive robustness analysis to demonstrate that our results are not limited to a single data split or initialization. By varying random seeds across multiple runs, we evaluate the stability of each model with respect to algorithm initialization and the selection of training data subsets. This demonstrates that the observed accuracy is consistent and not the result of a specific, favorable configuration. This framework offers a promising approach to accelerating circuit design across technology nodes by reducing simulation costs while maintaining accuracy in predicting performance.

This work proposes a prototype system for utilizing nitrogen-vacancy center-based quantum sensing for generalized threat detection systems. Changes to the operation or environment of an IC will cause differences in the magnetic field emanations, which can be detected through changes in a spin-state-dependent photocurrent within a diamond. Threat detection circuitry can be integrated within the sensitive CMOS IC itself at a high spatial resolution for real-time monitoring and spatially resolved low-overhead protections. The key contributions of this work are the CMOS and NV center system for high magnetometer sensitivity while maintaining CMOS design flexibility, the novel security application for quantum sensing, and the proposed method of heterogeneous integration for a complete system.

Ingestible electronics offer a noninvasive way to monitor important physiological signals from the gastrointestinal (GI) tract, which may open a new era in healthcare. However, it faces challenges with energy constraints and data privacy. Attacks on unprotected wireless communication can result in dangerous outcomes. In addition, conventional cryptography schemes are proven vulnerable to quantum computer attacks. Previous works either do not ensure post-quantum security or overlook the need for low energy consumption. Thus, we propose an ultra low-power hardware solution which is post-quantum secure protocol for an ingestible device. First, by combining Lightweight Cryptography (LWC) and mutually authenticated key exchange (MAKE) in Post-Quantum Cryptography (PQC), we reduce the energy consumption of enc/decryption by 59.12/61.42% by using LWC and that of key exchange with mutual authentication 75.82% by not including expensive post-quantum secure digital signature algorithm. In addition to the proposed protocol, we take a duty-cycling approach with a timer to wake the device from deep sleep mode (consuming less than 0.00025 mA). Based on our analysis for a practical scenario, we show that the overhead of cryptographic operations is compensated by using duty-cycling resulting in the lowest energy mode in hardware. Even when calling the most expensive cryptographic operation, PQC-based key exchange, for each data communication session, we can save energy by at least 67.66×.

Traditional approaches for designing analog circuits are time-consuming and require significant human expertise. Existing automation efforts using methods like Bayesian Optimization (BO) and Reinforcement Learning (RL) are suboptimal and costly to generalize across different topologies and technology nodes. In our work, we introduce a novel approach, LEDRO, utilizing Large Language Models (LLMs) in conjunction with optimization techniques to iteratively refine the design space for analog circuit sizing. LEDRO is highly generalizable compared to other RL and BO baselines, eliminating the need for design annotation or model training for different topologies or technology nodes. We conduct a comprehensive evaluation of our proposed framework and baseline on 22 different OpAmp topologies across four FinFET technology nodes. Results demonstrate the superior performance of LEDRO as it outperforms our best baseline by an average of 13% FoM improvement with 2.15× speed-up on low-complexity Op-Amps and 48% FoM improvement with 1.7× speed-up on high-complexity Op-Amps. This highlights LEDRO’s effective performance, efficiency, and generalizability.

This paper presents the first fully integrated on-chip sub-THz retro-backscatter CMOS circuit, operating at 263 GHz. Using the Van Atta reflector principle and a signal swapping and mode-conversion electromagnetic structure, the design achieves retro-directive operation with a 3-dB angle availability of $105^{\circ} / 82^{\circ}$. Fabricated in an Intel-16 CMOS process, the prototype demonstrates BPSK modulation over an input power range of -7 dBm to -13.9 dBm at 263 GHz, exhibiting a measured conversion loss of $\mathbf{1 2}$ dB and capability of Mbps-level data rate at $5-\mathrm{cm}$ reader-to-chip distance. These findings validate a low-cost, low-power, wide-angle THz retro-backscatter solution, improving the performance and practicality of ultra-miniaturized tag applications.

We present a V-band fractional-N cascaded PLL achieving the integrated jitter of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$58.3\text{fs}_{\text{rms}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{J}}$</tex> of-250.2dB. A fully differential voltage domain quantization (Q)-noise cancellation of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage reference sampling PLL suppresses the Q-noise of the delta-sigma modulator <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta\Sigma \mathrm{M})$</tex> with <0.92LSB INL and <0.08mV resolution while only consuming 0.62mW. The 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-stage sub-sampling PLL features a 0.82mW switched capacitor frequency-to-voltage converter-based FLL, addressing a harmonic lock issue without a power-hungry mmWave frequency divider. Its frequency re-acquisition time is within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.42\mu \mathrm{s}$</tex>.

We present an ML-driven framework for predicting circuit performance metrics, bridging the gap between schematic and layout simulations, multi-process corner analysis, and measured silicon data. We focus on 14nm and 5nm FinFET-based ring oscillators, collecting data across varying supply voltages, temperatures, and process corners. Using three baseline ML models—XGBoost, Random Forest, and a Neural Network—we simulate real-world design scenarios where parameter fine-tuning may not always be feasible. Key tasks include predicting layout performance from schematic data, performance prediction across process corners, and predicting measured chip performance via transfer learning. Our results show that these models can achieve less than 5% mean absolute percentage error (MAPE) for power and frequency prediction while reducing required simulations by more than 2×. In migrating from 14nm to 5nm, XGBoost and Neural Network achieve high accuracy (>0.99 R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) using just 10% of 5nm simulations. This framework offers a promising approach to accelerating circuit design across technology nodes, reducing simulation costs while maintaining accuracy in predicting performance.

The global AI market is growing explosively with the rise of generative AI applications, such as image manipulation and text-to-text/image/video creation. AI was primarily expected to automate only simple tasks like classification and data analysis. However, the advent of generative AI has transformed it into a creativity assistant, helping people think more creatively by offering new perspectives through deep neural networks (DNNs). As shown in Fig. 23.6.1, there are various types of DNNs used in generative AI, which can be categorized into two groups: non-diffusion models (NDMs) and diffusion models (DMs). NDMs, such as variational autoencoders (VAEs), generative adversarial networks (GANs), and transformers, are still predominantly used. DMs require 25–100x more operations due to their need for iterative inference (INF). Consequently, generative AI processors need to efficiently accelerate both NDMs and DMs.

Digital in-memory compute (IMC) architectures allow for a balance of the high accuracy and precision necessary for many machine learning applications, with high data reuse and parallelism to reduce energy consumption. However, one often overlooked parameter is security, which is necessary to maintain the privacy and integrity of the accelerator. In this work, we propose an IMC macro design that is protected against two types of eavesdropping attacks, passive physical side-channels and memory bus-probing. This is achieved through secure compute that eliminates the need for random bits, local model decryption with a lightweight cipher, and secret key generation reusing existing IMC circuitry. These contributions provide side-channel security against all practical attackers beyond 1 million samples, while still operating without any effect on neural network accuracy at 8.1 TOPS/W energy efficiency.

Audio denoising is crucial for delivering high-quality sound in applications ranging from communication devices to entertainment systems. On-device denoising is critical for en-suring consistent performance across various host platforms. Machine learning (ML) models exhibit strong audio processing performance in the frequency domain but require efficient hardware design. This paper focuses on enhancing audio quality using convolutional encoder-decoder ML models with low power consumption while meeting real-time processing constraints. We achieve this by developing a quantized network that optimally reduces computational costs without compromising enhancement quality. Furthermore, our hardware quantization scheme reduces memory usage by up to 75% while maintaining accuracy. Next, we design a complementary processing element activation routing scheme tailored to our algorithm, significantly reducing the on-chip memory accesses by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5}-\mathbf{9}\times$</tex>. Fabricated in 28nm CMOS process, our chip demonstrates real-time audio denoising, processing each frame within 8ms while consuming only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$407\ \mathbf{\mu} \mathbf{W}$</tex> or 3.24 μJ/frame at 0.65V, 18.5 MHz, making it ideal for battery-powered IoT devices. In terms of performance, our chip also achieves the highest evaluation score for audio quality (PESQ), outperforming previous works.

This work presents a low-power reconfigurable 12T-SRAM current-domain analog in-memory computing (IMC) SRAM macro design to address non-linearities, process variations, and limited throughput. The proposed design features a time-domain subthreshold multiply and accumulate (MAC) operation with a differential output current sensing technique. Reconfigurable current-controlled design supports different precisions and speeds. A 1kbit macro is prototyped in a 14-nm CMOS process and achieves a measured bitwise energy efficiency of 580 TOPS/W while obtaining highly linear MAC operations. This is the highest energy efficiency reported for IMC current-domain computing methods. In addition, simulation results and estimations based on blocks and 1kb macro measurements show that increasing the macro size to 16kbit can achieve 2128 TOPS/W, which is comparable to other charge domain computing methods. Finally, A fully analog MLP classifier for voice-activity detection (VAD) is prototyped with 3 cascaded analog IMC macros, achieving ~ 90% classification accuracy at 5dB-SNR while consuming 0.58 nJ/classification.

With the rising adoption of deep neural networks (DNNs) for commercial and high-stakes applications that process sensitive user data and make critical decisions, security concerns are paramount. An adversary can undermine the confidentiality of user input or a DNN model, mislead a DNN to make wrong predictions, or even render a machine learning application unavailable to valid requests. While security vulnerabilities that enable such exploits can exist across multiple levels of the technology stack that supports machine learning applications, the hardware-level vulnerabilities can be particularly problematic. In this article, we provide a comprehensive review of the hardware-level vulnerabilities affecting domain-specific DNN inference accelerators and recent progress in secure hardware design to address these. As domain-specific DNN accelerators have a number of differences compared to general-purpose processors and cryptographic accelerators where the hardware-level vulnerabilities have been thoroughly investigated, there are unique challenges and opportunities for secure machine learning hardware. We first categorize the hardware-level vulnerabilities into three scenarios based on an adversary’s capability: 1) an adversary can only attack the off-chip components, such as the off-chip DRAM and the data bus; 2) an adversary can directly attack the on-chip structures in a DNN accelerator; and 3) an adversary can insert hardware trojans during the manufacturing and design process. For each category, we survey recent studies on attacks that pose practical security challenges to DNN accelerators. Then, we present recent advances in the defense solutions for DNN accelerators, addressing those security challenges with circuit-, architecture-, and algorithm-level techniques.

Text and spoken language have become standard ways to interface with edge devices. Due to tight power and compute constraints, they require efficient natural language processing that can adapt the computation to the hardware conditions. This paper presents a Transformer accelerator running a custom-trained SuperTransformer model from which SubTransformers of various sizes can be sampled enabling adaptive model configuration. The test chip contains a variable-depth adder tree to support different model dimensions, a word elimination unit to prune redundant tokens, and dedicated softmax and layer normalization units. It achieves up to 6.9× scalability in network latency and energy between the largest and smallest SubTransformers, under the same operating conditions. Word elimination can reduce network energy by 16%, with a 14.5% drop in F1 score. At 0.68V and 80MHz, processing a 32-length input with our custom 2-layer Transformer model for intent detection and slot filling takes 0.61 ms and 1.6 μJ.

The rapid growth of the Internet of Things (IoT) demand ultralow power wireless systems. This article presents a 3.5 GHz Citizens Broadband Radio Service (CBRS) band wireless energy harvesting backscatter system, optimized for sensitivity and start-up time, making it ideal for fast inventory counts and extensive coverage in IoT-enabled warehouses. The system features a rectifier with −31 dBm sensitivity for 0.9 V output, enabling quick energy storage within ~20 s from cold start. It employs backscattering blocks consuming 120 nW power with improved uplink data transfer resiliency to reduce minimize time. Incorporating a current-starved oscillator and self-clocked signal encoding, our design replaces low-dropout regulator (LDO) with a PTAT-current source inside backscattering/communication blocks to cut power consumption, while also boosting PVT-resiliency. Fabricated in TSMC 65 nm CMOS, the chip outperforms existing solutions in area and power efficiency. This comprehensive system not only boosts the capabilities of battery-free IoT tags but also opens new avenues for their application in industrial and commercial settings, paving the way for the next generation of IoT devices.

Traditional approaches for designing analog circuits are time-consuming and require significant human expertise. Existing automation efforts using methods like Bayesian Optimization (BO) and Reinforcement Learning (RL) are sub-optimal and costly to generalize across different topologies and technology nodes. In our work, we introduce a novel approach, LEDRO, utilizing Large Language Models (LLMs) in conjunction with optimization techniques to iteratively refine the design space for analog circuit sizing. LEDRO is highly generalizable compared to other RL and BO baselines, eliminating the need for design annotation or model training for different topologies or technology nodes. We conduct a comprehensive evaluation of our proposed framework and baseline on 22 different Op-Amp topologies across four FinFET technology nodes. Results demonstrate the superior performance of LEDRO as it outperforms our best baseline by an average of 13% FoM improvement with 2.15x speed-up on low complexity Op-Amps and 48% FoM improvement with 1.7x speed-up on high complexity Op-Amps. This highlights LEDRO's effective performance, efficiency, and generalizability.

In this work, we present a reconfigurable edge sensing system leveraging monolithic three-dimensional (3D) integration to integrate tens of thousands of sensors directly over conventional silicon CMOS circuitry, fabricated entirely within major commercial semiconductor manufacturing facilities. Owing to the dense and fine-grained 3D integration, our demonstrated IC can rapidly adapt its architecture to trade-off spatial sampling resolution, temporal sampling resolution, and bit resolution optimized to the current environment sensed by the chip. Within milliseconds, the chip can modulate the amount of data captured per sensing operation by >2,000X, corresponding with a >16,000 range in power consumption. While this demonstration integrates carbon nanotube (CNT)-based FETs (CNFETs) as gas sensing elements on the upper-layer of the chip, this reconfigurable edge sensing IC can be implemented with a wide variety of emerging sensing technologies and thus is a platform for future intelligent sensing at the edge.

= 25) within 3.2 min, showcasing its potential to dramatically improve survival rates and combat the opioid epidemic.

In the evolving field of biomedical engineering, ingestible devices have emerged as pivotal tools for healthcare monitoring within the human gastrointestinal (GI) tract. This paper addresses challenges in communication, emphasizing the selection of the 2.4 GHz band and proposing a Bluetooth Low Energy (BLE)-compatible wake-up receiver (WuRx) operating at 2.48 GHz that validates with the in-vivo test. An LNA-first receiver is used to counter signal loss within the GI tract and achieves -81 dBm of sensitivity. The proposed design incorporates a low-power single clock chain with a Film Bulk Acoustic Resonator (FBAR) and a duty cycling scheme for reducing power consumption. The average power with 1% duty cycling ratio is 0.11 µW. This work introduces the first BLE-compatible WuRx for low power ingestible devices, demonstrating the potential for diverse medical applications.

Fully homomorphic encryption (FHE) is a cryptographic technology with the potential to revolutionize data privacy by enabling computation on encrypted data. Lately, the CKKS FHE scheme has become quite popular because it can process real numbers. However, CKKS computing is not pervasive yet because it is resource-intensive both in terms of compute and memory, and is multiple orders of magnitude slower than computing on unencrypted data. The recent algorithmic and hardware optimizations to accelerate CKKS computing are promising, but CKKS computing continues to underperform due to an expensive operation known as bootstrapping. While there have been several efforts to accelerate bootstrapping, it continues to remain the main performance bottleneck. One of the reasons for this performance bottleneck is that unlike the non-bootstrapping parts of CKKS computing the bootstrapping algorithm is inherently sequential and exhibits interdependencies among the data. To address this challenge, in this paper, we introduce HEAP an accelerator that uses a hybrid scheme-switching approach. HEAP uses the CKKS scheme for the non-bootstrapping steps, but switches to the TFHE scheme when performing the bootstrapping step of the CKKS scheme. The hybrid approach transitions to the TFHE scheme by extracting coefficients from a single RLWE ciphertext to represent multiple LWE ciphertexts. We incorporate the bootstrapping function into the TFHE BlindRotate operation and simultaneously apply the BlindRotate operation to all LWE ciphertexts. A parallelized execution of bootstrapping is then feasible because there are no data dependencies between distinct LWE ciphertexts. With our approach, we require smaller-sized bootstrapping keys leading to about $18 \times$ less amount of data to be read from the main memory for the keys. In addition, we introduce a variety of hardware optimizations in HEAP—from modular arithmetic level to NTT and BlindRotate datapath optimizations. The approach in HEAP is agnostic of the hardware and can be mapped to any system with multiple compute nodes. To evaluate HEAP, we implemented it in RTL and mapped it to a single FPGA system and an eight-FPGA system. Our comprehensive evaluation of HEAP for the bootstrapping operation shows a $15.39 \times$ improvement when compared to FAB. Similarly, evaluation of HEAP for the logistic regression model training shows $14.71 \times$ and $11.57 \times$ improvement when compared to FAB and FAB-2 implementations, respectively.

The IoT's expansion calls for ultra-low power wireless systems. With 6G on the horizon, wireless energy harvesting backscatter paves the way for improved energy efficiency and enhanced connectivity, without conventional batteries and high-power radios. Despite licensed spectrum scarcity, the telecom industry explores deploying backscattering technology in licensed bands due to higher transmitter power and advanced interference management [1]. Past research on RF energy harvesters emphasized enhancing the rectifier sensitivity for heavily duty-cycled applications but lacked the ultra-low power backscattering circuits [2]–[4]. Others [5], [6] have advanced backscattering technology but sacrificed sensitivity and active communication power <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\approx 10-30\mu\mathrm{W})$</tex> , burdening the wake-up charging time at low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(&lt; -30\text{dBm})$</tex> available power levels. This is especially critical in IoT-enabled warehouses where swift inventory counting is essential (Fig. 1 top) with broad coverage. Furthermore, the form factor should be minimized to validate the batteryless harvesters. The pursuit, therefore, continues to design a comprehensive system running at higher 5G frequencies (hence lower form-factor) that combines high sensitivity, simple backscattering communication and thus, low start-up times.

Machine learning (ML) accelerators provide energy efficient neural network (NN) implementations for applications such as speech recognition and image processing. Recently, digital IMC has been proposed to reduce data transfer energy, while still allowing for higher bitwidths and accuracies necessary for many workloads, especially with technology scaling [1], [2]. Privacy of ML workloads can be exploited with physical side-channel attacks (SCAs) or bus probing attacks (BPAs) [3] (Fig. 1). While SCAs correlate IC power consumption or EM emissions to data or operations, BPAs directly tap traces between the IC and off-chip memory. The inputs reflect private data collected on loT devices, such as images of faces. The weights, typically stored off-chip, reveal information about proprietary private training datasets. This work presents the first IMC macro protected against SCAs and BPAs to mitigate these risks.

Embedded neural network (NN) implementations are vulnerable to misclassification under fault attacks (FAs). Clock glitching and injecting strong electromagnetic (EM) pulses are two simple yet detrimental FA techniques that disrupt the NN by: 1) introducing errors in the NN model and 2) corrupting NN computation results. This article introduces the first application-specific integrated circuit (ASIC) demonstration of an energy-efficient NN accelerator equipped with built-in FA detection capabilities. We have integrated lightweight cryptography-based checks for on-chip verification to identify model errors and additionally serve as a fault detection sensor for spotting computational errors. We showcase high error-detection capabilities along with a minimal area overhead of 5.9% and negligible impact on NN accuracy.

RFID technologies have been widely deployed in supply-chain management for logistics tracking and goods integrity. Recently, millimeter-wave and sub-THz carriers are used to enable on-chip antenna integration and hence packageless, miniature RFID form factors. In [1], a 4.4mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip with 24GHz downlink and 60GHz uplink is presented. In [2], the tag size is further reduced to 1.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by pushing the carrier frequency to 260GHz. While these tiny tags allow for non-intrusive labeling, they still share one drawback with other RFIDs in anti-counterfeiting of goods (Fig. 12.5.1): if an RFID (even if the ID itself is unclonable) is detached from the genuine item and reattached to a fake item, the authentication fails. Unlike in other anti-tampering digital systems, the low power, cost and size budgets in RFIDs pose great challenges to implementing effective anti-tampering capabilities. Current solutions are based on fragile packaging materials that can easily break if physical tampering occurs [3–4]. This mechanism is, however, not reliable (e.g. under gentle or solvent-assisted detachments, and the damage can be recovered) and prevents the monolithic integration and tag miniaturization shown in [1–2]. In comparison, the anti-tampering is significantly enhanced if the fingerprinting for tampering detection is inherent to the “attachment” itself, such as the random glue distribution and the roughness of the item surface, which are very difficult to clone. Based on this principle, in this paper, we present a monolithic tag chip that utilizes a sub-THz wave not only to perform uplink/downlink communications with a compact 4.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> tag size, but also to detect tampering through the unique sub-THz wave scattering at the chip-item interface with random variation at tens to hundreds of μm scale (Fig. 12.5.1).

This letter explores security vulnerabilities in sparsity-aware optimizations for Neural Network (NN) platforms, specifically focusing on timing side-channel attacks introduced by optimizations such as skipping sparse multiplications. We propose a classification prediction attack that utilizes this timing side-channel information to mimic the NN's prediction outcomes. Our techniques were demonstrated for CIFAR-10, MNIST, and biomedical classification tasks using diverse dataflows and processing loads in timing models. The demonstrated results could predict the original classification decision with high accuracy.

We introduce a continuous-time (CT) pipeline analog-to-digital converter (ADC) featuring a time-interleaved sub-ADC-digital-to-analog converter (DAC) path in its first stage. The proposed sub-ADC-DAC path enhances the ADC’s bandwidth by improving the signal cancellation at the summing node of the first stage. In addition, we have developed an inductorless delay line for the first stage, improving the amplitude and phase matching, thus minimizing the input signal leakage into the backend ADC. Furthermore, the theoretical jitter limitations in the CT pipeline architecture have been explored, and the proposed theory is compared against the measured results. The prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves a peak signal-to-noise ratio (SNR) of 61.7 dB at low frequencies and 60.8 dB at high frequencies across a 1-GHz bandwidth. The active area of the ADC is 0.77 mm2, and it consumes 240 mW. The Schreier figure of merit (FOM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{S}$ </tex-math></inline-formula> ) is 157.9 dB, which is amongst the best for CT ADCs with bandwidth greater than 500 MHz.

This article presents the first sub-terahertz (sub-THz) wake-up receiver (WuRx) for ultra-miniaturized, massively deployable platforms. A detector-first architecture, utilizing a pseudo-differential cold-FET-based CMOS THz detector, is employed to reduce power consumption. The THz front end employs a dual-antenna-feed detector topology, independently driving the gate and drain of a transistor, thus achieving the optimal conditions of the device for low noise-equivalent power (NEP). In addition, the WuRx incorporates a low-power cryptographic authentication engine to enhance security, preventing the denial-of-sleep (DoSL) attacks through token randomization in a lightweight cryptographic algorithm. Implemented in a 65-nm CMOS process, the 264-GHz system, including four on-chip patch antennas, occupies an area of 1.54 mm2. It achieves a sensitivity of −48 dBm while consuming 2.9- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> dc power in the continuous mode. Wireless tests with multi-meter range and electrical beam-steering operation of sub-THz transponder are provided to demonstrate the feasibility of THz connectivity for the next-generation Internet of Things (IoT).

Cloud computing has made it easier for individuals and companies to get access to large compute and memory resources. However, it has also raised privacy concerns about the data that users share with the remote cloud servers. Fully homomorphic encryption (FHE) offers a solution to this problem by enabling computations over encrypted data. Unfortunately, all known constructions of FHE require a noise term for security, and this noise grows during computation. To perform unlimited computations on the encrypted data, we need to perform a periodic noise reduction step known as bootstrapping. This bootstrapping operation is memory-bound as it requires several GBs of data. This leads to orders of magnitude increase in the time required for operating on encrypted data as compared to unencrypted data.