Kenneth E. Goodson

Passive cooling devices like heat pipes and vapor chambers utilize a capillary-driven liquid–vapor phase change loop to spread extreme heat flux from localized hotspots in microprocessors. Their performance is often limited by capillary transport mechanisms, which dictate fluid routing through their internal wick structures. This study presents a simple technique to create rough, hierarchical pin-fin microstructure arrays using a UV-laser cutter and compares transport rates in these hybrid wicks against analogously shaped, plasma-etched, smooth surfaces to investigate enhanced capillary action. One-dimensional capillary wicking experiments demonstrate increased rates of capillary filling, up to 117%, and two models are developed to evaluate these results. An empirical power-law-based model connects the magnitude of wicking enhancement to the aspect ratio and nondimensional interpillar gap of each wick design, predicting increased transport rates between sample types with an 8% error. A simple naïve force enhancement model derived from first principles prescribes a roughness factor that predicts the change in wicking rates with a 10% error. Though neither model captures the outlier behavior observed in exceptional aspect ratios─ tall, densely packed pillars or short, widely spaced patterns─divergent flow mechanisms are delineated beyond 1 < AR < 6, and roughness effects on capillary flow are herein reported as a starting point for further fundamental studies.

Next-generation memory-on-logic 3D systems have the potential for significant performance improvements, such as lower latency and higher bandwidth. However, stacking memory layers on top of logic layers impedes heat removal from a 3D chip stack, limiting computational power and memory bandwidth. Introducing a secondary liquid-cooled heat sink that removes heat on the package substrate side of a 3D system can significantly reduce the junction temperature of the logic layer (processor). Nevertheless, its implementation requires careful analysis of the interactions between the flow distribution of the cooler and non-uniform heat generation in a 3D system. We perform a high-fidelity conjugate thermal-flow simulation at the package level to identify hot spots, enabling the development of embedded cooling solutions. This approach involves modeling with multiple levels of detail (LODs) that reduces memory requirements and simulation time, enabling a computational fluid dynamics (CFD) analysis to be performed, replacing the commonly used approach of assigning an effective heat transfer coefficient (HTC). We explored the feasibility of double-sided cooling, where an embedded pin-fin array cooler is inside the silicon interposer or the package substrate. The double-sided cooling can reduce the maximum junction temperature by up to 45 °C compared to the baseline single-sided cooling (135 °C vs. 90 °C), ensuring the temperature constraints of the logic chips and memory stacks (105 °C and 95 °C, respectively) are met. Integrating a bottom heat sink in the package substrate is more feasible for fabrication, but additional thermal resistance from the C4 bump layer results in a higher processor temperature compared to the design using a Silicon interposer-embedded cooler, requiring a higher flow rate (Qtop = 5 LPM, Qbottom = 0.45 LPM) and, therefore, large pressure drop (~150 kPa), and a dedicated Coolant Distribution Unit (CDU) design is required for such configuration.

Rising power densities in power electronics demand cooling solutions that can sustain high local heat fluxes while maintaining low thermal resistance and high energy efficiency. This work presents the design, computational fluid dynamics (CFD)-based optimization, and experimental validation of a single-phase liquid cooled copper U-type manifold microchannel cooler (MMC) for high-heat-flux power electronics. A conjugate heat-transfer CFD framework, driven by multi-point hotspot heat maps, is used in a sequential multi-objective optimization of manifold and microchannel geometries to minimize junction-to-fluid thermal resistance and pressure drop, thereby maximizing coefficient of performance (COP). The resulting optimized MMC geometry is then fabricated and experimentally characterized using discrete GaN devices on a PCB as heat sources in an indirect-cooling configuration. Across flow rates of 0.5-6 L min −1 , the optimized design reduces pressure drop by 70–98% and lowers average thermal resistance by 19–26% relative to its baseline MMC design, while increasing COP by up to 74 × for a comparable heat removal rate. The optimal cooler design dissipates heat fluxes up to 208 W cm −2 with COPs as high as 1.6 × 10 6 and low thermal resistance. Extrapolation of the measured performance to a 75 mm × 75 mm package footprint indicates a junction to coolant thermal resistance as low as 3.5 K kW −1 , providing substantial thermal headroom for multi-kilowatt power modules and GPU-class packages. Our work demonstrates that single-phase liquid cooled copper MMCs designed using Pareto-based optimization in an indirect-cooling configuration provide a practical, high-COP solution for high-heat-flux electronics. • Hotspot-driven multi-objective numerical optimization of U-type manifold microchannels. • Optimization targets enhanced thermal-hydraulic performance with improved COP. • Experimental validation using discrete GaN power devices as heat sources. • Sustained single-phase cooling up to 208 W cm −2 with COP up to 1.6 × 10 6 . • 70-98% lower pressure drop, 19-26% lower thermal resistance, and up to 74 × COP improvement compared with baseline MMC designs.

This paper presents the first 1.2 kV, 2.2 mΩ half-bridge SiC power module with double-sided cooling utilizing embedded microchannel coolers (u-Coolers) for automotive traction applications. The laser-cut, co-sintered u-Coolers are integrated into DBC substrates, eliminating thermal interface materials and reducing junction-to-coolant resistance. The module achieves a thermal resistance as low as 0.076 K/W at 2 L/min fluid rate, enabling the module level of 3.94 kW heat dissipation with 25 °C coolant as inlet. Experimentally, the thermal performance of 0.10 K/W at 0.5 L/min is measured, closely matching the simulation. A fixture-assisted assembly process ensures precise alignment and mechanical robustness, while electrical testing confirmed low conduction loss with 2.2 mΩ Rds(on) at 25 °C. Compared to state-of-the-art automotive modules, the proposed design reduces thermal resistance by up to 62.5% and provides a scalable, manufacturable double-sided cooling solution for next-generation high-power-density traction inverters.

High-power logic and RF devices in 3D integration face severe thermal challenges, with localized hot spots exceeding 2 kWcm⁻². In-situ electroplated copper/diamond composite utilizing diamond microparticles (10 to 100 μm), are emerging as viable solution to reduce the device junction temperature. There have been very few reports on direct measurements of individual diamond particles and the thermal boundary conductance (TBC) at the metal–diamond interface — parameters essential for predictive modeling and design. Using time-domain thermoreflectance (TDTR), we characterized the thermal conductivity of ~20 μm and ~80 μm single-crystal diamond particles to be 1366<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-187.5</sub><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+191.9</sup> and 774. 6<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-104.3</sub><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+106.8</sup> W m⁻¹K⁻¹, with edge thermal conductivity suppression of 38% and 53%, respectively. We further developed a 2D gray-phonon Monte Carlo model with diffuse boundary scattering, which reproduced the experimental trends of size- and edge-dependent thermal Zconductivity suppression even in defect-free crystals, demonstrating that geometric confinement and quasi-ballistic transport alone can generate apparent reductions in thermal conductivity. Additionally, we report thermal boundary conductance (TBC) between~20 μm and ~80 μm single-crystal diamond particles and Al transducer (76 and 180 nm, respectively) to be 128. 5<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9.304</sub><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+9.435</sup> to 189. 5<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13.97</sub><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+14.36</sup> MW m⁻²K⁻¹. We conducted detailed confidence interval analysis that revealed large uncertainties remain due to strong parameter coupling, showing that thermal conductivity and TBC cannot always be uniquely resolved. Nonetheless, even assuming constant TBC, the thermal conductivity continues to decrease approaching particle edge, underscoring the influence of boundary effects. Beyond these observations, several limitations must be recognized: the thermal penetration depth can exceed the finite particle thickness, leading to additional uncertainties; using conventional TDTR fitting may be inappropriate for finite boundary samples; particle morphology and impurity gradient could introduce additional uncertainty. Together, these findings provide benchmark data and highlight the experimental challenges of TDTR on diamond microparticles, pointing to the need for improved models and measurement strategies for reliable design of Cu/diamond composite heat spreaders.

Abstract Thermal interface materials (TIMs) play a crucial role in thermal management in modern electronics, where minimizing overall thermal resistance is critical for reliable and efficient operation. Among various advanced TIMs, composites such as copper nanowires embedded in polydimethylsiloxane (CuNWs/PDMS) show great promise due to their high thermal conductivity and high mechanical compliance. However, thermal characterizations in previous studies have often been limited by poor thermal contact at the interfaces between TIMs and adjacent substrates, which introduces significant measurement uncertainties. In this work, we present a high-precision thermal characterization technique using infrared (IR) cross-sectional microscopy for CuNWs/PDMS composite TIMs. To overcome the limitations of dry contact resistance, we apply thin layers of a gallium-based liquid metal (LM) at the interfaces, which significantly reduce the interfacial thermal resistance from ∼10−4 to 1.4 × 10−6 m2K/W. When used with a 1 mm-thick silicon reference wafer, this configuration achieves an effective thermal resistance of (3.23±0.6) × 10−6 m2K/W for the CuNWs/PDMS composite. Theoretical analyses suggest the potential for achieving even lower thermal resistance values with optimized LM wetting thickness.

Abstract The increasing demand for high-performance computing has accelerated the development of three-dimensional integrated circuits (3DICs), which offer enhanced performance but pose significant thermal challenges due to greater heat flux and more complex thermal pathways. This study explores the feasibility of phase change material (PCM)–Si/Cu composites for transient thermal management in 3DICs. To validate its effectiveness, we fabricated, characterized, and evaluated the PCM–Si pin-fin composites (a size of 50 × 50 μm2, a pitch of 100 μm, and a height of 150 μm). A custom-built experimental setup enabled simultaneous electrothermal, infrared (IR), and high-speed optical imaging, allowing in-depth quantitative analysis of phase transition dynamics under pulsed heat flux conditions. The results confirmed that PCM–composite systems are particularly effective for short-duration heat pulses, well before reaching steady-state conditions, achieving up to a ∼20% reduction in peak junction temperature (e.g., from ∼88 °C to ∼71 °C in representative tests). 3D finite-element simulations revealed that most of the vertical heat flow is conducted through the high-conductivity scaffold (Si pin fins), while lateral conduction from the Si pin fins into the PCM enables efficient utilization of latent heat during rapid transients, effectively buffering temperature spikes. The fundamental timescale-dependent behavior and phase change dynamics observed in this work are expected to apply to other PCM-enhanced cooling systems with a high-conductivity scaffold, particularly in applications with high-frequency thermal cycling over the PCM's phase change temperature, although specific timescales will depend on the material properties, geometry, and operating conditions. The present work provides a framework for development of PCM–copper nanowire (CuNW) composite thermal interface materials (TIMs) with the capability to suppress temperature spikes in timescales &amp;lt; 1 ms. To this end, we have also demonstrated the infiltration process for phase change material into the CuNWs matrix.

Abstract The continuing increase in central processing unit and graphic processing unit performances can be attributed mostly to the rise in frequency, scaling of chip area (bigger dies), advancements in thermal management, and improvements in thermal design power, among other factors. Over the past two decades, the size of a typical graphic processing unit die has increased from 100 mm2 to ∼800 mm2 in the year 2020. Silicon-based single-phase embedded microchannels with a large area of 30 mm × 30 mm, featuring three-dimensional (3D) manifold (MF) μ-coolers, can potentially remove heat and minimize pressure drop. However, previous computational fluid dynamics simulation findings indicated considerable temperature nonuniformity resulting in increased thermal resistance and maximum temperature. The primary cause of temperature nonuniformity is the abrupt flow acceleration at the entrance and sudden deceleration at the end section of the 3D-manifold inlet channels. This leads to a significant temperature rise in the middle region of the microcooler. In this study, we introduce innovative microcooler designs and conduct extensive computational fluid dynamics simulation to achieve low thermal resistance, low-pressure drop, and crucially, uniform temperature distribution across the entire surface area of the microprocessor. To deal with this issue, our initial approach involved integrating converging inlet and diverging outlet channels into the 3D manifold. Although this method effectively dealt with nonuniformity throughout the μ-cooler's area, it still resulted in a large pressure drop. Consequently, we implemented a narrow opening at the end of the inlet channels in the 3D manifold. This allows a portion of the coolant (50–80%) to bypass the microchannels in the cold plate to the exit plenum. As a result, the pressure was reduced by ∼66% compared to the conventional 3D manifold microchannel cooler.

Abstract Engineered microporous structures have received much attention in high-heat-flux electronics cooling due to their high thermal conductivity and permeability, and large surface area for heat transfer, but are susceptible to boiling-induced thermal degradation. This study investigates the efficacy of nickel inverse opals (NiIOs) in mitigating structural degradation caused by corrosion-assisted erosion during pool boiling with water as the working fluid. First, we compared the reliability of NiIOs to copper inverse opals (CuIOs) for a 3-day pool boiling test at constant heat flux. The NiIOs demonstrated superior resistance to thermal degradation due to their inherent corrosion resistance and mechanical strength. Subsequently, we conducted a more controlled experiment to show the effect of heat flux on the degradation of the NiIOs while excluding the effect of temperature variations. Pool boiling tests of 20-μm-thickness NiIOs covering an area of ∼11 × 11 mm2 with a 2.5 × 2.5 mm2 heater at the center were conducted at heat flux levels of 20%, 40%, and 60% of the critical heat flux (CHF) for 3 days. The NiIOs subjected to heat flux levels of 20% and 40% CHF showed minimal degradation, while the sample subjected to 60% CHF showed erosion on the top surface due to higher bubble formation and departure rate. These results show the potential of NiIOs as a promising solution for long-term thermal management in high-power electronic devices, although design considerations for maximum allowable heat flux are necessary for reliable operation.

Amorphous oxide semiconductors, such as indium tin oxide (ITO), have gained attention for their largescale, low-temperature deposition, making them attractive for back-end-of-line (BEOL) integration [1–4]. Recently, gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) [2–4] with oxide channels have shown promise for driving BEOL-integrated memories, such as magnetoresistive random access memory (MRAM) [2]. However, oxides have low thermal conductivity, and temperature rise during operation of high-performance access transistors could adversely affect reliability [5, 6]. The thermal characteristics of GAA NSFETs with ITO channel have not been explored, to date.

In this study, a comparative performance analysis is conducted between conventional two-phase forced convection cooling (pumped) and capillary-based cooling. Both types of microcoolers employ silicon micropin fin structures with dimensions of $\mathbf{5} \times \mathbf{5} \mathrm{mm}^{2}$ (diameter: $11 \mu \mathrm{~m}$, spacing: $20 \mu \mathrm{~m}$, height: $100 \mu \mathrm{~m}$) integrated into two types of three-dimensional manifold. For the pumped twophase flow microcooler, a 3D-printed manifold is utilized, achieving a heat flux of approximately $950 \mathrm{~W} / \mathrm{cm}^{2}$, a superheat of $\sim \mathbf{2 0}^{\circ} \mathbf{C}$ (base $\mathbf{T}_{\text {sat }} \sim \mathbf{1 1 2}^{\circ} \mathbf{C}$), a flow rate of 77 $g / m i n$, and a vapor exit quality of $x_{e} \sim 0.06$. In contrast, the capillary-based two-phase microcooler employs a “capillary-based” copper wire mesh 3D manifold, achieving a heat flux of $\sim 500 \mathrm{~W} / \mathrm{cm}^{2}$ with a superheat of $\sim 7^{\circ} \mathrm{C}$ (base $\mathrm{T}_{\text {sat }} \sim 100^{\circ} \mathrm{C}$) resulting in a heat transfer coefficient of $500,000 \mathrm{~W} / \mathrm{m}^{2}-{ }^{\circ} \mathrm{C}$ with a flow rate of $3 \mathrm{~g} / \mathrm{min}$, and $x_{\mathrm{e}} \sim 1$. It is noteworthy that the flow rate required for the capillarybased cooling system is only one-tenth of that needed for the conventional two-phase cooling system. Additionally, this study reports the thermal instability and pressure drops for both cooling methods.

Capillary-driven boiling using the microporous structures exhibits an exceptional two-phase heat transfer performance due to the presence of numerous nucleation sites and effective liquid-vapor separation. In addition, the high capillary pressure due to the small pore size enables passive liquid supply. Therefore, capillary-driven boiling is a promising candidate for energy-efficient microcoolers in high-heat-flux electronics. However, achieving area scalability is challenging due to significant viscous pressure losses along the wick, which hinder liquid transport across the boiling region. This limitation poses a major obstacle to contemporary large-area, high-performance chip cooling solutions and requires the development of the area-scalable capillary-driven two-phase cooler. In the present study, we have significantly improved the performance and expanded the cooling area of a capillary-driven micro-cooler with the augmented microporous layers over “sparse” and “dense” micro pin arrays to improve the two-phase heat transfer coefficient in conjunction with a capillary-based silicon open microchannel manifold (channel spacing of $\mathbf{5 7 0, 1 1 4 0}$ and $\mathbf{1 7 1 0 ~} \boldsymbol{\mu} \mathbf{m}$), for efficient liquid delivery and vapor extraction, targeting exit vapor quality, $x_{\mathrm{e}} \approx 1$. Infrared thermography is employed to characterize the spatial temperature distribution and to understand the underlying heat and mass transfer mechanism. To extract the contribution of the two-phase heat transfer from the applied heat flux, the flow rate at the drainages in the test vehicle is measured to estimate the boiling rate at the critical heat flux level. We demonstrated critical heat flux level $\approx 200 \mathrm{Wcm}^{-2}$ and a superheat of $\approx 4^{\circ} \mathrm{C}$, achieving heat transfer coefficient $\approx 430 \mathrm{kWm}^{-20} \mathrm{C}^{-1}$ and $x_{\mathrm{e}} \approx 1$ with minimum inlet flow rates of $5 \mathrm{~g}^{(\mathrm{min})^{-1}}$. Even a higher CHF level of $\approx 450 \mathrm{Wcm}^{-2}$ with superheat $\approx 7^{\circ} \mathrm{C}$, is achieved using inlet flow rate of $15 \mathbf{g}(\mathbf{m i n})^{-1}$ but with $x_{e} \approx 0.65$. The 3D manifold with microchannels spacing of $1140 \mu \mathrm{~m}$ provided the right balance of efficient liquid delivery for capillary wicking and open pathways for vapor extraction, showing the highest critical heat flux, given the same supplied flow rate. The two-phase cooler assisted by capillary-driven boiling in the previous studies typically supplied liquid across the perimeter of the wick, limiting their scalability and performance. The integration of a silicon microchannel manifold with a copper inverse opal porous layer overcomes these limitations by enhancing liquid flow distribution and preventing local dryout, enabling efficient two-phase heat transfer over larger areas. Therefore, the two-phase cooling scheme in this study demonstrates large-area capillary-driven boiling without compromising high heat transfer efficiency, making it a promising solution for contemporary high-performance chip cooling.

Two-phase embedded microcoolers are emerging as a promising solution to high-performance and highly efficient cooling for microprocessors and power electronics. We characterized a silicon microchannels capillary-driven microcooler coated with hydrophilic copper dendritic microstructure, achieving two-phase boiling at heat flux level $\gt350 \mathrm{~W} / \mathrm{cm}^{2}$ and a small superheat $\left(\sim 10^{\circ} \mathrm{C}\right)$, leading to a heat transfer coefficient of $300,000 \mathrm{~W} / \mathrm{m}^{2}-{ }^{\circ} \mathrm{C}$ (or $\mathrm{R}^{\prime \prime}=0.03 \mathrm{~cm}^{2}- { }^{\circ} \mathrm{C} / \mathrm{W}$). To provide additional insight into the physics of capillarydriven boiling, bubble dynamics, and dry-out formation, we conducted IR thermal and high-speed flow visualization imaging. An important finding is related to the delayed dry-out of $\sim 300 \mathrm{~ms}$ in capillary-based microcoolers compared to a much shorter timescale of 2 to 10 ms for the two-phase pumped flow in smooth silicon microchannels. The result demonstrates the potential of the capillary-based two-phase cooler for transient thermal management. For future work, the improvement in liquid delivery will be considered by implementing 2D microchannels, optimizing the microchannel dimensions, in particular width and spacing, and introducing hydrophilic copper dendritic microstructure at the walls of the microchannels.

The substrate-embedded two-phase cooler is a promising solution for power modules, cooling multiple high heat flux (350 $W / c m^{2}$) chips with small superheat ($\sim 10^{\circ}$ C), leading to very small evaporation thermal resistances of $0.03 \mathrm{~cm}^{2}-{ }^{\circ} \mathrm{C} / \mathrm{W}$ (Lin et al., InterPACK 2024) and satisfying the cooling requirement of the power electronics with high power density. Our previous work characterized the capillary-based microcooler at atmospheric pressure (100 kPa at $T_{\text {sat }}=100^{\circ} \mathrm{C}$), where the higher boiling point of water at $100^{\circ} \mathrm{C}$ limits the maximum heat flux and its application to the device with a lower temperature limit. If the two-phase micro cooler can operate at sub-atmospheric pressure $\sim 25 \mathrm{kPa}$ ($T_{\text {sat }}=65 { }^{\circ} C$), there is a potential for lowering the boiling temperature and increasing the maximum heat flux.In this study, we investigate the performance of a capillary-driven evaporator using a semi-closed loop at sub-atmospheric pressures of 25,65, and 100 kPa. A microchannel-embedded copper substrate is used to emulate the DBC-based evaporator for the two-phase cooling tests, and a cold plate is used as the condenser. A maximum heat removal rate of $550 \mathrm{~W} / \mathrm{cm}^{2}$ is achieved under the vacuumed pressure of 25 kPa. The proposed platform demonstrates the feasibility of operating an embedded capillary-based two-phase cooler using water coolant under a sub-atmospheric environment for optimized cooling performance.

The next generation of high heat flux electronics demand thermal interface materials (TIMs) that balance excellent thermal conductivity with mechanical compliance. This paper focuses on the fabrication and characterization of silicon pin fin and liquid metal (PFLM) composites with target thermal resistance of $1 \mathrm{~mm}^{2} \mathrm{KW}^{-1}$. We micropatterned silicon pin fin wicks ($55 \mu \mathrm{~m}$ thickness, $41-96 \%$ porosity, $1 \times 1 \mathrm{~cm}$ footprint) infiltrated with liquid metal (LM). We utilized high spatial resolution IR cross-sectional microscopy to map the temperature profile, achieving measurement sensitivity of less than $1 \mathrm{~mm}^{2} \mathrm{KW}^{-1}$. To quantify variability between TIMs due to assembly and coppergallium interfacial reactions, we stacked three PFLM composite samples for each measurement. We measured thermal resistances from $2.2 \pm 0.8 \mathrm{~mm}^{2} \mathrm{KW}^{-1}(41 \% \mathrm{LM}-59 \% \mathrm{Si})$ to $5.2 \pm 0.9 \mathrm{~mm}^{2} \mathrm{KW}^{-1} (96 \% \mathrm{LM}-4 \% \mathrm{Si})$. The results are in good agreement with a onedimensional (1D) conduction model and mark a reduction of up to a third from a $51 \mu \mathrm{~m}$ thick LM TIM without pin fins ($\mathbf{3. 2 5} \pm \mathbf{1. 2 4} \mathrm{mm}^{2} \mathrm{KW}^{-1}$). We further show the pin fins precisely control the thickness of the LM. Future work should focus on optimizing the pin fin geometry and making the TIMs resistant to gallium corrosion.

The 3D chip integration and packaging of high-power logic and RF devices is constrained by strict junction temperature limits, especially with hot spots exceeding $1 \mathrm{kWcm}^{-2}$. There is an urgent need for cost-effective heat spreaders with thermal conductivities above that of copper. This work proposes the development of a Diamond/Cu Alloy heat spreader by in-situ electroplating copper through diamond particles in the range of 10 to $100 \mu \mathrm{~m}$. The thermal conductivity and boundary conductance of diamond microparticles were investigated using time-domain thermoreflectance (TDTR). Measurement sensitivity was examined by calculating sensitivity coefficients for various fitting methods, and the relationship between these coefficients and the resulting measurement standard deviations was experimentally verified. Measurements were performed on monocrystalline diamond particles of $\sim 70 \mu \mathrm{~m}$ and $\sim 20 \mu \mathrm{~m}$, examining thermal properties at the center and edge. While a significant decrease in thermal conductivity was observed as the measurement spot moved from the center to the edge-suggesting greater phonon scattering near boundaries-this suppression effect may also arise from the fact that the 2 D radial heat conduction model for the TDTR data fitting does not account for the finite geometry of the diamond particle. For $\sim 70 \mu \mathrm{~m}$ and $\sim 20 \mu \mathrm{m}$ particles, the thermal conductivity dropped by 38% and 53%, respectively. The boundary conductance ranged from $187.2 \pm 57.3$ to $191.0 \pm 50.4 \mathrm{MWm}^{-2} \mathrm{~K}^{-1}$, with one outlier ($\sim 20 \mu \mathrm{~m}$ at the edge). High uncertainties remain, partly due to low sensitivity at short time delays. Future work will include simulations to separate boundary scattering effects from boundary conditions and optimize transducer thickness.

Abstract Heterogeneous integration of electronics is critical to the next wave of electronics applications ranging from extremely power dense energy conversion systems to advanced chiplet and copackaged optics architectures for next-generation computing. Enhanced functionality and operation are essential goals in heterogeneous integration. In all applications, effective thermal management of both active and passive electronic devices is required to support these goals. Additive manufacturing (AM) opens new avenues for heterogeneous integration of electronics. This article thus provides a review of AM methods and applications in the specific context of thermal solutions for heterogeneous integration of electronics. Three-dimensional printing methods, associated materials (e.g., metal, polymer, ceramic, and composite), and electronics package integration approaches, or conceptual fabrication workflows, are outlined for cold plates, heat sinks, fluid flow manifolds, and thermal interface materials (TIMs) plus composites for electronics. The current status of design optimization methods for AM of thermal solutions for electronics is also covered. Future challenges and research directions are outlined to further stimulate the development of advanced manufacturing methods, novel design techniques, and unique electronics package integration capabilities for thermal solutions.

Triply periodic minimal surface (TPMS) metamaterials show promise for thermal management systems but are challenging to integrate into existing packaging with strict mechanical requirements. Composite TPMS lattices may offer more control over thermal and mechanical properties through material and geometric tuning. Here, we fabricate copper-plated, 3D-printed triply periodic minimal surface primitive lattices and evaluate their suitability for battery thermal management systems. We measure the effects of lattice geometry and copper thickness on pressure drop, mechanical properties, and thermal conductivity. The lattices as internal filling structures in a multichannel cold plate exhibited pressure drops under 6.5 kPa at a 1 LPM flow rate. Pressure drop decreased when the number of channels (width of the cold plate) was increased. With a 0.43% copper volume loading, the lattice more than tripled in thermal conductivity but still retained a polymer-like compliance. A higher lattice relative density did not affect the thermal conductivity but caused a higher elastic modulus and compressive strength, and a stiffer cyclic loading response. The lattice design demonstrates that the structural parameters that control pressure drop, mechanical, and thermal conductivity can be decoupled, which can be used to achieve a wide range of disparate properties in complex multiphysics systems.

• Combination of a porous surface with a mesh manifold is tested in pool fed boiling. • Copper mesh separates and guides liquid and vapor flow above boiling surface. • Maximum heat flux of 490 W/cm 2 is dissipated at wall superheat of 36 °C in water. • Greater than 65% critical heat flux increase over porous surface alone. High-performance electronics are continuously demanding cooling of higher heat fluxes. Phase-change cooling, including pool boiling, is a useful approach to address this challenge; however, competition between liquid and vapor flows generally limit the heat fluxes that can be dissipated. A range of strategies to control these flows have been investigated previously, including capillary guides. Here a manifold structure formed from a metallic mesh is investigated to control the disposition of liquid and vapor phases above a pool fed boiling surface enhanced with porous structures. Copper mesh forms defined liquid flow paths, using capillary action to guide and distribute liquid evenly over the heated surface, along with open channels to facilitate vapor escape. The mesh provides a novel structure for liquid guidance that imposes low resistance to liquid flow while occluding a minimal area of heated surface underneath. The manifold performance is characterized in boiling fed by a pool of water above a laser-textured aluminum nitride heat dissipation surface with pin–fin structures having heights of 110 µm and spacing of 30 µm with a heated area of 5 mm x 5 mm. A maximum heat flux of 490 W / c m 2 is reached with the manifold in the pool fed configuration, representing an increase of more than 65% over the porous pin fin surface alone. The maximum stable superheat observed for the manifold of 36 K is 14 K higher than that for the porous surface without the manifold. The factors limiting performance of the manifold are analyzed. High superheat is attributed to partial flooding of the boiling surface as suggested by the reduction in superheat using external suction. Similar systems and structures for enhanced two-phase cooling are compared.

Magnetic tunnel junctions (MTJs) with ultrathin MgO tunnel barriers are at the heart of magnetic random-access memory (MRAM) and exhibit potential for spin caloritronics applications due to the tunnel magneto-Seebeck effect. However, the high programming current in MRAM can cause substantial heating which degrades the endurance and reliability of MTJs. Here, we report the thermal characterization of ultrathin CoFeB/MgO multilayers with total thicknesses of 4.4, 8.8, 22, and 44 nm, and with varying MgO thicknesses (1.0, 1.3, and 1.6 nm). Through time-domain thermoreflectance (TDTR) measurements and thermal modeling, we extract the intrinsic (∼3.6 W m –1 K –1 ) and effective (∼0.85 W m –1 K –1 ) thermal conductivities of annealed 1.0 nm thick MgO at room temperature. Our study reveals the thermal properties of ultrathin MgO tunnel barriers, especially the role of thermal boundary resistance, and contributes to a more precise thermal analysis of MTJs to improve the design and reliability of MRAM technologies.

Abstract Engineered microporous structures have received much attention in high-heat-flux electronics cooling due to their high thermal conductivity and permeability, and large surface area for heat transfer, but are susceptible to boiling-induced thermal degradation. This study investigates the efficacy of nickel inverse opals (NiIOs) in mitigating structural degradation caused by corrosion-assisted erosion during pool boiling with water as working fluids. First, we compared the reliability of NiIOs to copper inverse opals (CuIOs), for a 3-day pool boiling test at constant heat flux. The NiIOs demonstrated superior resistance to thermal degradation due to their inherent corrosion resistance and mechanical strength. Only partial oxidation was observed on NiIOs surface while CuIOs structures were completely diminished after 3 days. Subsequently, we conducted a more controlled experiment to show the effect of heat flux and bubble dynamics on the degradation of the NiIOs. To exclude the effect of temperature variations, pool boiling reliability tests of 20-μm-thickness NiIOs covering ∼10 × 10 mm2 with a 2.5 × 2.5 mm2 heater at the center were conducted at heat flux levels of 20%, 40%, and 60% of the critical heat flux (CHF) for 3 days. The NiIOs subjected to heat flux levels of 20% and 40% CHF showed minimal degradation while the top surface of the NiIOs subjected to 60% CHF underwent some erosion, possibly due to a higher bubble formation and departure rate. These results show the potential of NiIOs as a promising solution for long-term thermal management in high-power electronic devices, although design considerations for maximum allowable heat flux are necessary for reliable operation. The next step is to repeat the reliability tests for &amp;gt; 30 days while monitoring the changes in surface temperature, NiIOs structure, and bubble dynamics over a longer period.

Abstract The continuing increase in CPU and GPU performances can be attributed mostly to the rise in frequency, scaling of chip area (bigger dies), advancements in thermal management, and improvements in thermal design power, among other factors. Over the past two decades, the size of a typical GPU die has increased from 100 mm2 to ∼800 mm2 in the year 2020. Silicon-based single-phase embedded microchannels with a large area of 30 mmx30 mm, featuring three-dimensional (3D) manifold (MF) μ-coolers, can potentially remove heat and minimize pressure drop. However, previous computational fluid dynamics (CFD) simulation findings indicated considerable temperature nonuniformity resulting in increased thermal resistance and maximum temperature. The primary cause of temperature non-uniformity is the abrupt flow acceleration at the entrance and sudden deceleration at the end section of the 3D-manifold inlet channels. This leads to a significant temperature rise in the middle region of the microcooler. In this study, we introduce innovative microcooler designs and conduct extensive computational fluid dynamics (CFD) simulations to achieve low thermal resistance, low-pressure drop, and crucially, uniform temperature distribution across the entire surface area of the microprocessor. To deal with this issue, our initial approach involved integrating converging inlet and diverging outlet channels into the 3D manifold. Although this method effectively dealt with the nonuniformity throughout the u-cooler’s area, it still resulted in a large pressure drop. Consequently, we implemented a narrow opening at the end of the inlet channels in the 3D manifold. This allows a portion of the coolant (50–80%) to bypass the microchannels in the cold plate to the exit plenum. As a result, the pressure was reduced by ∼66% compared to the conventional 3D manifold microchannel cooler.

Abstract This work details high-precision thermal characterization of CuNWs-PDMS composite TIMs using infrared (IR) cross-sectional microscopy. To enhance measurement sensitivity and to reduce the thermal resistances across TIM tester components and sample, we apply thin layers of high thermal conductivity gallium-based liquid metal (LM) to reduce the dry contact thermal interface resistances from ∼10−4 to 1.4 × 10−6 m2KW−1. Application of the LM in combination with a 1 mm thick silicon wafer as the reference layer, yields thermal resistance of ∼(3.23 ± 0.6) × 10−6 m2KW−1 for the CuNWs/PDMS composite. Theoretical analyses suggest the potential for achieving even lower thermal resistance values with optimized LM wetting thickness while the accuracy of the measurements can be further improved by pattering a heater on the backside of the 1 mm thick silicon reference substrate.

Abstract We have developed a silicon-based capillary-enhanced two-phase micro-cooler capable of removing a high heat flux &amp;gt; 200 Wcm−2 with water mass flow rate ≈ 28 g(min)−1 (vapor quality, xe ≈ 0.8) over a large area ≈ 2 cm × 2 cm at superheat &amp;lt; 20 °C, resulting in a thermal resistance of phase change, R″mean,2-ϕ ≈ 0.08 cm2°CW−1. By increasing the flow rate to ≈ 150 g(min)−1, a hybrid single/two phase regime prevails resulting in a critical heat flux ≈ 285 Wcm−2 (1.1 kW/chip) with minimal pressure drop ≈ 10 kPa, achieving 100× larger Coefficient of Performance (COP), compared to the conventional forced convective microchannel cooling. In this work, we utilize dense silicon channel fin array (height 100 μm, width 15 μm and 15 μm spacing) as capillary wicking structure in combination with a 3D silicon open-microchannel manifold (channel width and period ≈ 100 μm and 570 μm, respectively) for capillary-based liquid delivery and vapor extraction over large, heated area of 2 cm × 2 cm. The micro-cooler performs the best at low flow rates and high heat fluxes where the capillary flow and two-phase boiling dominates, resulting in a very uniform temperature distribution over the large area of the micro-cooler. At the high flow rates (pressurized flow), the coolant bursts out of the gap between the 3D manifold and the cold plate, resulting in single-phase cooling near the inlets of the micro-cooler. The temperature profile and its uniformity, or lack thereof, strongly depend on the competing effects of the single-phase and two-phase cooling regimes, which in turn depend on the flow rate and applied heat flux.

Abstract Effective thermal management is crucial in power module design, significantly influencing the cost, performance, and reliability of the traction inverters. As we strive for greater power density and smaller form factors, innovative thermal solutions become imperative. In this study, we explore a two-phase cooling method enabled by substrate-embedded microchannels for the power module. We utilize surface enhancement features at the substrate microchannels to enable capillary-driven flow for passive liquid supply. We find that the two-phase cooling in our study leads to a high heat flux removal rate of 400 W/cm2 at a low superheat of 10 °C. Moreover, the coolant flow rate is less than 1 g/min, nearly 50 times lower than the pumped flow-based two-phase microcoolers. We also investigate the implementation of the two-phase cooling method into a power module-like package. A systematic study of packages with 1 and 4 chips is conducted and verified with the simulation. The impact of the condenser and vapor recovery features on the cooling performance is also studied. The proposed two-phase cooler can overcome the typical issues encountered in two-phase cooling, such as flow instability and dry-out.

Understanding the limits of spatio-temporal carrier dynamics, especially in III-V semiconductors, is key to designing ultrafast and ultra-small optoelectronic components. However, identifying such limits and the properties controlling them has been elusive. Here, using scanning ultrafast electron microscopy (SUEM), in bulk n-GaAs and p-InAs, we simultaneously measure picosecond carrier dynamics along with three related quantities: sub-surface band bending, above-surface vacuum potentials, and su

Abstract A virtual testbed simulation framework is created for the economic, reliability, and lifetime analysis of battery thermal management control strategies in electric vehicles (EVs). The system-level model is created in the MATLAB environment using the Simscape library and custom components are developed as required. A lumped parameter coupled electrothermal model with temperature and state of charge (SOC)-dependent cell parameters is adopted from the literature to characterize battery performance. Suitable cell capacity degradation models are implemented to capture the cycle aging and calendar aging of the battery. The economic benefit of extending the lithium iron phosphate (LFP) battery lifetime by optimal thermal conditioning is weighed against the corresponding energy cost of the operation allowing for the assessment and adoption of economy-conscious strategies under different conditions. Active cooling of the battery using a vapor compression system along with a preconditioning strategy is benchmarked against passive cooling by a radiator for operating cost, battery lifetime, and net cost savings. Active cooling with precooling before fast charging can maintain optimal battery temperature but requires an additional electricity cost of 170–530 $/year, compared to passive cooling. However, the added cost is more than compensated for by the increase in battery lifetime by 1.4–1.9 years leading to a net saving of 140–550 $/year.

While magnetoresistive random-access memory (MRAM) stands out as a leading candidate for embedded nonvolatile memory and last-level cache applications, its endurance is compromised by substantial self-heating due to the high programming current density. The effect of self-heating on the endurance of the magnetic tunnel junction (MTJ) has primarily been studied in spin-transfer torque (STT)-MRAM. Here, we analyze the transient temperature response of two-terminal spin–orbit torque (SOT)-MRAM with a 1 ns switching current pulse using electro-thermal simulations. We estimate a peak temperature range of 350–450 °C in 40 nm diameter MTJs, underscoring the critical need for thermal management to improve endurance. We suggest several thermal engineering strategies to reduce the peak temperature by up to 120 °C in such devices, which could improve their endurance by at least a factor of 1000× at 0.75 V operating voltage. These results suggest that two-terminal SOT-MRAM could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering. These insights are pivotal for thermal optimization strategies in the development of MRAM technologies.

Abstract Aluminum nitride (AlN) is a promising material for thermal management in 3D integrated circuits (ICs) due to its high thermal conductivity. However, achieving high thermal conductivity in AlN thin films grown at low temperatures on amorphous substrates poses significant challenges for back‐end‐of‐line (BEOL) compatibility. This study reports high cross‐plane thermal conductivities approaching 90 Wm −1 K −1 for sub‐300 nm‐thick AlN films sputter‐deposited at low temperatures (&lt;200 °C) on ordinary SiO 2 substrates. The correlations between cross‐plane and in‐plane thermal conductivity, texture, grain size, oxygen content, Al:N atomic ratio, and thermal boundary conductance of these films are explored. These findings reveal the crucial role of grain orientation alignment in achieving high thermal conductivity and high thermal boundary conductance. A method is introduced to effectively monitor the thermal conductivity of the AlN thin films using X‐ray diffraction. This study offers valuable insights that can aid in the implementation of an effective thermal management material in the semiconductor production line.

Maintaining reasonable operating temperature for large area high heat flux microprocessors in data centers and power electronics has emerged as a major engineering challenge. Recently, we have developed a high-performance area scalable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-cooler using capillary-driven boiling in copper inverse opals (CIOs) by designing a 3-D manifold for liquid distribution and vapor extraction. The underlying concept takes advantage of the high heat flux capillary-driven boiling of random-packed CIOs, and minimized the overall pressure drop by incorporating a silicon-based 3-D manifold structure. In this work, we have developed physics-based heat transfer and fluid dynamics modeling platform, through which we address the importance of co-design of the CIO morphology and the manifold geometry and elucidate the optimized CIO wick and manifold geometry for maximum critical heat flux (CHF) of the CIO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-cooler. The effective wicking length in CIO, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ L_{\text {eff}}$ </tex-math></inline-formula>, which is the longest distance for the liquid to travel inside the porous media, is a critical co-design parameter for the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-cooler to achieve the highest overall CHF, lowest superheat, and sufficient liquid delivery supply over the large area microprocessor. The modeling results indicate that CHF of up to 1013 W/cm2 can be achieved for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-cooler size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> mm2 with the co-optimization of the CIO morphology and the manifold geometry.

Abstract Ultra‐wide bandgap semiconductor AlGaN is a promising candidate for high‐power and high‐frequency electronics. AlGaN‐heterostructures with nitrogen (N)‐polarity can offer added benefits of low‐leakage and large drive current. However, electro‐thermal transport in such heterostructures remains unexplored, although they are essential for electronic device functionality. Here, the thermal and electrical properties of N‐polar Al x Ga 1‐x N‐channel heterostructures (Al percentage, x = 15–90%) are explored and compared with their GaN counterpart. The thermal measurements uncover that the effective thermal resistance of the thin channel and barrier layers are similar in magnitudes for N‐polar‐ AlGaN and GaN heterostructures, however, the total effective thermal conductivity in N‐polar AlGaN heterostructure is ≈4× smaller. This reduction originates from the larger thermal resistance of the thick Al 0.15 Ga 0.85 N buffer layer within the AlGaN stack. N‐polar Al x Ga 1‐x N stack displays a thermal conductivity almost independent of temperature, measured from room temperature up to 200 °C. Hall measurements of an N‐polar Al 0.30 Ga 0.70 N‐channel heterostructure further reveal that electrical properties such as resistivity, carrier density, and mobility remain nearly unchanged with temperature, indicating the dominance of alloy‐phonon scattering in such material systems. These results offer important insights into material‐device co‐design and reliability of N‐polar AlGaN heterostructures.