Samuel Graham

We report on the design and experimental demonstration of ultra-wide-bandgap AlGaN polarization-graded field-effect transistors (PolFETs) with ultra-thin channels aimed at enabling high current capability, RF performance, and reduced thermal resistance. Polarization-graded AlGaN layers and ultra-thin pseudomorphic AlGaN buffer layers are employed to achieve low thermal resistance while maintaining high structural quality. The demonstrated PolFETs achieve a maximum soft-saturation drain current density of 800 mA/mm at VG = 4 V and ∼500 mA/mm at VG = 0 V, along with current- and power-gain cutoff frequencies (fT/fmax) of 26/28 GHz, respectively. Small-signal modeling was performed to analyze parasitic and transit delays, and gate-resistance thermometry was implemented to characterize device thermal behavior and benchmark against state-of-the-art AlGaN HEMTs. The ultra-thin AlGaN PolFET exhibits a thermal resistance of 12 K mm/W, representing a significant reduction compared to conventional AlGaN transistor structures. These results demonstrate the feasibility of polarization-engineered ultra-wide-bandgap AlGaN transistors for RF and mm-wave applications, with the added advantage of improved thermal performance.

Next-generation high-power radio-frequency (RF) devices increasingly demand transistors that operate efficiently with high gain at high frequencies. High-aluminum-content ultra-wide-bandgap (UWBG) AlGaN alloys have shown great potential for enabling such high-frequency RF technologies. However, the widespread adoption of AlGaN-based RF devices is limited by thermal-management challenges arising from the intrinsically low thermal conductivity of AlGaN, which leads to higher device thermal resistance for a given geometry compared to GaN RF devices. As a result, these next-generation devices are highly susceptible to self-heating. This study investigates the thermal behavior of UWBG AlGaN devices, focusing on the effects of AlGaN channel thickness, substrate technology, and high-k material integration on reducing device thermal resistance to enable high-power operation. Experimental results demonstrate a record-low thermal resistance of 3.96 mm$\cdot$K/W when an AlN substrate is employed and the AlGaN channel thickness is reduced to 5 nm. These findings provide valuable insights into mitigating thermal limitations in UWBG devices through device-level engineering and the strategic integration of high-k materials.

Next-generation high-power radio-frequency (RF) devices increasingly demand transistors that operate efficiently with high gain at high frequencies. High-aluminum-content ultra-wide-bandgap (UWBG) AlGaN alloys have shown great potential for enabling such high-frequency RF technologies. However, the widespread adoption of AlGaN-based RF devices is limited by thermal-management challenges arising from the intrinsically low thermal conductivity of AlGaN, which leads to higher device thermal resistance for a given geometry compared to GaN RF devices. As a result, these next-generation devices are highly susceptible to self-heating. This study investigates the thermal behavior of UWBG AlGaN devices, focusing on the effects of AlGaN channel thickness, substrate technology, and high-k material integration on reducing device thermal resistance to enable high-power operation. Experimental results demonstrate a record-low thermal resistance of 3.96 mm$\cdot$K/W when an AlN substrate is employed and the AlGaN channel thickness is reduced to 5 nm. These findings provide valuable insights into mitigating thermal limitations in UWBG devices through device-level engineering and the strategic integration of high-k materials.

We report on the design and demonstration of ultra-wide bandgap AlGaN polarization-graded field effect transistors with ultra-thin channels to enable excellent current density and high-frequency performance while significantly reducing thermal resistance. We use polarization-graded AlGaN layers and ultra-thin pseudomorphic AlGaN buffer layers to enable low thermal resistance and excellent structural quality. The polarization-graded field effect transistors (PolFETs) demonstrated here show Imax over 800mA/mm and current/power gain cutoff frequency (fT/fmax) of 26/28 GHz. Small signal modeling and analysis were used to determine parasitic/transit delays, and gate-resistance thermometry was implemented to thermally characterize AlGaN PolFET and benchmark against state-of-the-art AlGaN HEMTs. The ultra-thin AlGaN PolFET showed thermal resistance of 12 K.mm/W, representing a significant reduction from typical AlGaN transistors. These results show state-of-art combination of high current density, excellent fT-LG product for ultra-wide bandgap AlGaN transistors, and superior thermal performance, and highlight the promise of AlGaN transistors for future RF and mm-wave applications.

We report on the design and demonstration of ultra-wide bandgap AlGaN polarization-graded field effect transistors with ultra-thin channels to enable excellent current density and high-frequency performance while significantly reducing thermal resistance. We use polarization-graded AlGaN layers and ultra-thin pseudomorphic AlGaN buffer layers to enable low thermal resistance and excellent structural quality. The polarization-graded field effect transistors (PolFETs) demonstrated here show Imax over 800mA/mm and current/power gain cutoff frequency (fT/fmax) of 26/28 GHz. Small signal modeling and analysis were used to determine parasitic/transit delays, and gate-resistance thermometry was implemented to thermally characterize AlGaN PolFET and benchmark against state-of-the-art AlGaN HEMTs. The ultra-thin AlGaN PolFET showed thermal resistance of 12 K.mm/W, representing a significant reduction from typical AlGaN transistors. These results show state-of-art combination of high current density, excellent fT-LG product for ultra-wide bandgap AlGaN transistors, and superior thermal performance, and highlight the promise of AlGaN transistors for future RF and mm-wave applications.

This paper reports an inter-laboratory comparison of the thermal characterization of GaN HEMTs using the gate resistance thermometry (GRT) technique. GRT test benches at three different universities in the United States are utilized to conduct GRT calibration and biased transistor measurements using best practices at each respective laboratory. The results in this work demonstrate excellent precision of GRT calibration and measurements - a critical assessment for ensuring accurate electrothermal modeling of GaN HEMTs. This work could be useful for GaN HEMT characterization and modeling engineers for determining the level of precision in GRT measurements and understanding discrepancies between GRT measurements collected at different laboratories.

Abstract Materials development is a complex task that may start with a predicted property for a material that exists only in a computer. To arrive at a maturity level for a specific application that will use the material requires substantial synthesis, scale-up, and testing to prove reliability, demonstrate that a new material has the required properties, and thereby gain the trust of the relevant design community. A multi-year process is typically required to reach such an end-state with many cases of failure along the way when funding runs out or an application imposes demands beyond the capability of a given material. This report proposes a framework of Materials Maturity Levels for such a development sequence that systematizes the various stages of materials development and maturation. A spreadsheet is provided as a checklist for evaluating or assessing the current maturity level of a material. The need is explained for increasing involvement of an intended application with advances in maturity, leading to an emphasis on the value of co-design (i.e., that the application and the material should be designed hand-in-hand because each affects the other). The extent to which any given material must be embedded in a composite structure is discussed because this is commonly required for electronic materials (more so than structural materials). Simulation of processing, microstructure, and properties at each level is crucial to track and accelerate the entire maturation process which is well described by the Materials Genome Initiative (MGI). Currently, simulation makes the strongest contribution to materials discovery but is expected to become increasingly useful for predicting development, processing, and manufacturing workflows. This, in turn, points out the importance of verification and validation (V&V) in software tools, as well as uncertainty quantification (UQ).

Abstract Silicon carbide (SiC) devices are increasingly favored in modern power modules, enabling significant size reductions while supporting higher power densities, resulting in heat fluxes exceeding 400 W/cm2. However, the time-varying loads typical in many applications induce substantial temperature cycling, posing thermo-mechanical challenges that necessitate cooling systems capable of handling peak loads. This study introduces a novel hybrid thermal management approach employing a three-component composite phase change material (PCM) integrated with standard liquid cooling to mitigate temperature cycling, lower peak junction temperatures, and extend the lifespan of power modules. The proposed PCM composition combines Field's metal (FM) with micro-encapsulated organic PCM (MEP) embedded within a graded porous honeycomb structure in the copper baseplate of the module. Transient thermal modeling is done under various time-varying loads and electric vehicle drive cycles, examining the effects of different times and duty factors. Results show a maximum temperature cycling reduction of 13.3% and 13.9% at heat transfer coefficients of 3000 W/m2 K and 4000 W/m2 K, respectively, compared to a power module with no PCM. Correspondingly, a power module lifecycle improvement of 120.1% and 112.5% is observed under these conditions. Thicker PCM-integrated baseplates improved transient performance due to higher thermal capacitance despite greater resistance. Additionally, FM-dominated PCM, with higher volumetric energy density, outperformed MEP-dominated PCM. These findings underscore the potential of a three-component composite PCM in power modules for superior transient thermal management and enhanced module durability.

Gate resistance thermometry (GRT) is a well-established electrical method that is used to infer the gate metal temperature of GaN high electron mobility transistors (HEMTs). In this work, the effect of the bottom side thermal boundary condition on the calibration of the temperature coefficient of resistance (TCR) and the measurement of the device temperature rise was investigated by applying GRT to a bare device die and an identical device die solder-bonded to a CuMo shim. It was found that the probing location of the thermocouple utilized during the calibration process can result in a 12% difference in the deduction of the TCR. Furthermore, the temperature rise of a GaN HEMT on a bare die with no thermal interface material between the bottom of the device die and the thermal stage could be $2.35 \times$ greater than a same device mounted to a CuMo shim due to wafer bow that results in a large thermal contact resistance. Therefore, proper experimental setup was found to be crucial in order to extract the correct TCR and temperature rise within GaN HEMTs with complex topside geometries where GRT is needed.

Conductive and radiative thermal transport play a critical role in the design, development, and performance of a wide array of technologies and applications. In this review, we focus on the challenges associated with nano- and microscale thermal measurements and the strategies developed thus far to overcome them. For measurements below ∼1,000°C, numerous thermoreflectance techniques are already in wide use; however, uncertainty and measurement error may limit the measurement of samples in certain regimes. These regimes include materials of high thermal conductivity (≳2,000 W/m·K), thin films (≲100 nm), or interfaces located well below the sample surface. A rigorous treatment of uncertainty and error is thus required for measuring these samples and for the development of future metrology tools. At higher temperatures, pyrometry techniques are being developed; however, several physical and experimental limitations exist. Some methods rely on a known emissivity for the measurement of temperature, and significant radiative transport can introduce error in modeling. Both of these mean that knowledge of spectrally dependent and temperature-dependent emissivity properties may be required.

Abstract. The DECOVALEX Task SAFENET is dedicated to advancing the understanding of fracture nucleation and evolution processes in crystalline rocks, with applications in nuclear waste management and geothermal reservoir engineering. Further improvements to fracture mechanics models are required in two distinct areas. Firstly, there is a need to enhance numerical methods for fracture mechanics under varying thermo-hydro-mechanical (THM) conditions. Secondly, there is a requirement to develop applied tools for performance and safety assessment in the context of nuclear waste management, as well as for reservoir optimisation in geothermal applications. Building on the achievements of SAFENET, which concentrated on benchmarking fracture models and experimental laboratory analyses, SAFENET-2 is dedicated to extending and validating models from the laboratory to the field scale. This paper gives a detailed description of the SAFENET-2 experimental programme work plan and modelling exercises. The experiments will be carried out at the rock mechanics laboratories of the University of Edinburgh and Chongqing University. For field data, the STIMTEC experiment at the Reiche Zeche teaching and research mine (Technische Universität Bergakademie Freiberg) is used. The individual steps of the Task are described in detail in this paper. As a result of SAFENET, the benchmark suite will be made available as interactive exercises via a web portal, thus promoting the concept of open science. The paper is a tool for teams to organise their work efficiently and is also an overview and insight for the community.

Ultrawide bandgap semiconductor aluminum nitride (AlN) possesses high thermal conductivity in bulk form due to long phonon mean-free-paths, high group velocity, and long lifetimes. However, the thermal transport scenario becomes very different in a thin AlN film due to phonon-defect and phonon-boundary scattering. Herein, we report experimental observation of ballistic to diffusive transition in a series of AlN thin films (1.6–2440 nm) grown on sapphire substrates. The ballistic transport is characterized by constant thermal resistance as a function of film thickness due to phonon scattering by defects and boundaries. In this transport regime, phonons possess very small group velocities and lifetimes. A gradual increase in the optical phonon lifetime is observed in the diffusive regime. Our study will aid the incorporation of highly conductive thin film materials in the semiconductor production line for efficient thermal management.

The electrothermal device performance of β-(Al0.21Ga0.79)2O3/Ga2O3 heterostructure field-effect transistors (HFETs) was enhanced by incorporating a 400 nm thick AlN capping layer via back-end-of-line room-temperature reactive sputter deposition. The AlN-capped HFETs demonstrated DC power densities >5 W/mm, higher than any previous report on lateral β-Ga2O3 transistors on native substrates. The breakdown voltage (VB) of the uncapped HFETs was 569 ± 250 V with a maximum VB of 947 V. For the AlN-capped HFETs, VB increased to 1210 ± 351 V with a maximum VB of 1868 V. The AlN-capped HFETs demonstrated a 27% reduction in device-level thermal resistance (RTH) as measured from the gate electrode. The combined use of electrical and thermal simulation helped elucidate the coupled electrothermal contributions to the measured reduction in the temperature rise for the AlN-capped HFETs. Although the measured AlN film thermal conductivity (13.3 ± 1.3 W/mK) was comparable to that of bulk β-Ga2O3, the capping layer still reduced the simulated peak channel temperature rise by ∼4% due to heat spreading only. Electrical simulation revealed that electric field spreading was an additional mechanism that contributed to the majority of the simulated 18% reduction in the peak channel temperature rise through delocalization and redistribution of the heat generation in the channel. Thermal modeling was used to evaluate further improvements in thermal performance that can be realized by optimizing the sputter deposition process to achieve thicker and higher thermal conductivity AlN.

Gallium nitride (GaN)-based radio frequency (RF) power amplifiers are spearheading the deployment of next-generation wireless systems owing to the large power handling capability at high frequencies and high-power-added efficiency. Unfortunately, this high power density operation leads to severe overheating, which reduces its lifetime and efficiency. Thus, correctly characterizing the temperature rise is of crucial importance to properly design GaN devices and cooling solutions. Optical-based thermometry techniques such as Raman thermometry and infrared (IR) thermography are commonly used to estimate the peak temperature rise, but they are limited by optical access, topside metallization, and depth averaging. Gate resistance thermometry (GRT) offers an alternative method to measure the temperature without needing optical access to the channel. Therefore, in this work, Raman thermometry is used in conjunction with GRT and electrothermal modeling to determine the accuracy of each method for a field-plated GaN high electron mobility transistor (HEMT) under various bias conditions. While both Raman thermometry and GRT measured a similar temperature rise under fully open (FO) channel conditions, it was found that GRT was better at estimating the peak temperature under a partially pinched-off (PPO) bias condition due to the source-connected field plate (SCFP) restricting optical access to the drain side of the gate edge.

Abstract This study investigates thermal transport across nanocrystalline diamond/AlGaN (aluminum gallium nitride) interfaces, crucial for enhancing thermal management in AlGaN‐based electronic devices. Chemical vapor deposition growth of diamond directly on AlGaN resulted in a disordered interface with a high thermal boundary resistance (TBR) of 20.6 m 2 ‐ KGW −1 . Sputtered carbide interlayers of boron carbide ( B 4 C ), silicon carbide ( SiC ), and a mixture of boron carbide and silicon carbide ( B 4 C / SiC ) are employed to reduce thermal boundary resistance in diamond/AlGaN interfaces. The carbide interlayers resulted in record‐low thermal boundary resistance values of 3.4 and 3.7 m 2 ‐ KGW −1 for Al 0.65 Ga 0.35 N samples with B 4 C and SiC interlayers, respectively. STEM imaging of the interface reveals interlayer thicknesses between 1.7 and 2.5 nm, with an amorphous structure. Additionally, Fast‐Fourier Transform (FFT) characterization of sections of the STEM images displayed sharp crystalline fringes in the AlGaN layer, confirming it is properly protected from damage from hydrogen plasma during the diamond growth. In order to accurately measure the thermal boundary resistance we develop a hybrid technique, combining time‐domain thermoreflectance and steady‐state thermoreflectance fitting, offering superior sensitivity to buried thermal resistances. The findings underscore the efficacy of interlayer engineering in enhancing thermal transport and demonstrate the importance of innovative measurement techniques in accurately characterizing complex thermal interfaces. This study provides a foundation for future research in improving thermal properties of semiconductor devices through interface engineering and advanced measurement methodologies.

Abstract. The DECOVALEX Task SAFENET is dedicated to advancing the understanding of fracture nucleation and evolution processes in crystalline rocks, with applications in nuclear waste management and geothermal reservoir engineering. Further improvement of fracture mechanics models is required in two distinct areas. Firstly, there is a need to enhance numerical methods for fracture mechanics under varying thermo-hydro-mechanical-chemical (THMC) conditions. Secondly, there is a requirement to develop applied tools for performance and safety assessment in the context of nuclear waste management, as well as for reservoir optimisation in geothermal applications. Building on the achievements of SAFENET, which concentrated on benchmarking fracture models and experimental laboratory analyses, SAFENET-2 is dedicated to extending and validating models from the laboratory to the field scale. This paper gives a detailed description of the work plan for Safenet-2 of the experimental program and the modeling exercises. The experiments will be carried out at the rock mechanics laboratories of the Universities of Edinburgh and Chongqing. For field data, the STIMTEC experiment at the Reiche Zeche teaching and research mine (Technische Universität Bergakademie Freiberg) is used. The paper gives a detailed description of the individual steps of the task. As a result of Safenet, the benchmark suite will be made available as interactive exercises via a web portal, thus promoting the concept of open science. The paper will help the teams to organize their work efficiently and also provide an overview and insight to the community.

This study investigates thermal transport across nanocrystalline diamond/AlGaN interfaces, crucial for enhancing thermal management in AlGaN/AlGaN-based devices. Chemical vapor deposition growth of diamond directly on AlGaN resulted in a disordered interface with a high thermal boundary resistance (TBR) of 20.6 m^2-K/GW. We employed sputtered carbide interlayers (e.g., $B_4C$, $SiC$, $B_4C/SiC$) to reduce thermal boundary resistance in diamond/AlGaN interfaces. The carbide interlayers resulted in record-low thermal boundary resistance values of 3.4 and 3.7 m^2-K/GW for Al$_{0.65}$Ga$_{0.35}$N samples with $B_4C$ and $SiC$ interlayers, respectively. STEM imaging of the interface reveals interlayer thicknesses between 1.7-2.5 nm, with an amorphous structure. Additionally, Fast-Fourier Transform (FFT) characterization of sections of the STEM images displayed sharp crystalline fringes in the AlGaN layer, confirming it was properly protected from damage from hydrogen plasma during the diamond growth. In order to accurately measure the thermal boundary resistance we develop a hybrid technique, combining time-domain thermoreflectance and steady-state thermoreflectance fitting, offering superior sensitivity to buried thermal resistances. Our findings underscore the efficacy of interlayer engineering in enhancing thermal transport and demonstrate the importance of innovative measurement techniques in accurately characterizing complex thermal interfaces. This study provides a foundation for future research in improving thermal properties of semiconductor devices through interface engineering and advanced measurement methodologies.

Abstract Advancing Silicon (Si) technology beyond Moore's law through 3D architectures requires highly efficient heat management methods compatible with foundry processes. While continued increases in transistor density can be achieved through 3D architectures, self‐heating in the upper tiers degrades the performance. Self‐heating is a critical problem for high‐power, high‐frequency, wide bandgap, and ultra‐wide bandgap devices as well. Diamond, known for its exceptional thermal conductivity, offers a viable solution in both these cases. Since thermal boundary resistance (between the channel/junction and diamond plays a crucial role in overall thermal resistance, this study investigates various dielectrics for interface engineering, such as Silicon dioxide (SiO 2 ), amorphous‐ Silicon Carbide (a‐SiC), and Silicon Nitride (SiN x ), to make a phonon bridge at gallium nitride (GaN)‐diamond and Si‐diamond interfaces. The a‐SiC interlayer reduces diamond/GaN (<5 m 2 K per GW) and diamond/Si (<2 m 2 K per GW) thermal boundary resistances by linking low‐ and high‐frequency phonons, boosting phonon transport through the interface. Engineered interfaces enhance heat spreading from the channel/junction and rule out premature failure.

The low thermal conductivity of β-Ga2O3 is a significant concern for maximizing the potential of this ultra-wide bandgap semiconductor as a power switching device technology. Here, we report on the use of nanocrystalline diamond (NCD) deposited via microwave plasma enhanced chemical vapor deposition (MP-CVD) as a top-side, device-level thermal management solution on a lateral β-Ga2O3 transistor. NCD was grown via MP-CVD on β-(AlxGa1−x)2O3/β-Ga2O3 heterostructures prior to the gate formation of the field-effect transistor. A reduced growth temperature of 400 °C and a SiNx barrier layer were used to protect the oxide semiconductors from etching in the MP-CVD H2 plasma environment. Raman spectroscopy showed a highly sp3-bonded NCD film was obtained at 400 °C, with grain size of about 50–100 nm imaged via atomic force microscopy. The incorporation of the NCD heat-spreading layer resulted in a β-(AlxGa1−x)2O3/β-Ga2O3 heterostructure field-effect transistor showing a decrease in the total thermal resistance at the gate by 42%. The fabrication process, including the NCD etch in the gate region, will need to be improved to minimize the impact of these processes on important device characteristics (i.e., drain current, threshold voltage, and leakage current).

Harnessing phase change materials (PCMs) for thermal management of power electronic devices shows potential to improve their reliability while decreasing the size, weight, power, and cost (SWaP-C) of the system due to the PCM’s high latent heat during solid-to-liquid transition. However, despite its high latent heat of fusion, PCMs are limited by their low thermal conductivity and a narrow operational temperature range near their melting point. We here numerically investigate the thermal buffering capability of three distinct compositions of a novel three-component composite PCM consisting of organic microencapsulated paraffin and metallic Fields metal with similar melting temperatures and copper cylindrical micropillars. These composites are evaluated under different single pulse width heating and cooling conditions and are benchmarked against a pure copper block. Results indicate that the composites generally surpass pure copper in minimizing peak device junction temperatures when the PCM undergoes phase change under single pulse loading, with the best performing composite consistently achieving a lower junction temperature than the copper block. The best performing composite can achieve up to 44% reduction in junction temperature swing compared to the copper reference when under a pulse train loading. These findings highlight the potential of the 3-component composite system as an effective thermal buffer for electronics subjected to transient heat loads.

Abstract A Ti 2 AlN MAX phase layered thin film electrode and oxygen getter layer for HfO 2 ‐based two‐terminal memristors is presented. The Ti 2 AlN/HfO x /Ti memristor devices exhibit enhanced resistive switching performance, including an ultra‐low reset current density (< 10 −8 M Ω cm 2 ), substantial on‐off ratio (≈ 6000), excellent multi‐level functionality (≈ 9 distinct states), impressive retention (up to 300 °C), and robust endurance (>200 million) as compared to conventional TiN and other alternative materials based memristors. Experimental measurements and modeling suggest that the distinctive combination of low thermal conductivity, high electrical conductivity, and unique ultra‐thin layer‐by‐layer structure of the Ti 2 AlN MAX phase thin film contribute to this exceptional performance with good reproducibility and stability. The results demonstrate for the first‐time the potential of this innovative sputtered MAX phase material for engineering energy‐efficient, high‐density non‐volatile digital, and analog memory devices aimed toward next‐generation sustainable artificial intelligence.

Heat dissipation plays a crucial role in the performance and reliability of high-power GaN-based electronics. While AlN transition layers are commonly employed in the heteroepitaxial growth of GaN-on-SiC substrates, concerns have been raised about their impact on thermal transport across GaN/SiC interfaces. In this study, we present experimental measurements of the thermal boundary conductance (TBC) across GaN/SiC interfaces with varying thicknesses of the AlN transition layer (ranging from 0 to 73 nm) at different temperatures. Our findings reveal that the addition of an AlN transition layer leads to a notable increase in the TBC of the GaN/SiC interface, particularly at elevated temperatures. Structural characterization techniques are employed to understand the influence of the AlN transition layer on the crystalline quality of the GaN layer and its potential effects on interfacial thermal transport. To gain further insights into the trend of TBC, we conduct molecular dynamics simulations using high-fidelity deep learning-based interatomic potentials, which reproduce the experimentally observed enhancement in TBC even for atomically perfect interfaces. These results suggest that the enhanced TBC facilitated by the AlN intermediate layer could result from a combination of improved crystalline quality at the interface and the "phonon bridge" effect provided by AlN that enhances the overlap between the vibrational spectra of GaN and SiC.

Highly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1±0.7 and 1.89±0.18 m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.

The impact of postbond annealing on the structural and thermal characteristics of 130 nm thick exfoliated (201) β-Ga2O3 (via H+ ion implantation) wafer bonded to (0001) 4H-SiC was studied. Thirty nanometer amorphous-Al2O3 was grown on the β-Ga2O3 substrates prior to bonding as an interlayer between β-Ga2O3 and 4H-SiC. The surface activated bonding technique was utilized for bonding, which induces a thin nanometer amorphous interfacial region at the bonded interface (Al2O3|4H-SiC). We demonstrate annealing the bonded structure at 800 °C up to 1 h is beneficial: (1) the removal of residual strain in the exfoliated β-Ga2O3 layer that was due to the exfoliation implant, (2) reduction of lattice mosaicity in the β-Ga2O3 layer, (3) nearly complete recrystallization of the amorphous bonded interfacial region, and (4) partial recrystallization of the initially amorphous-Al2O3 interlayer. The thermal characteristics correspondingly improve with the improvement in structural characteristics. The thermal conductivity of the as-bonded β-Ga2O3 layer was 2.9 W/m K, and the thermal boundary conductance of the bonded interface was 66 MW/m2 K. After annealing at 800 °C for 1 h, triple-axis x-ray diffraction ω:2θ measurements showed a reduction in strain for the β-Ga2O3 layer and the symmetric (201) rocking curve widths. We simultaneously observe a doubling of the β-Ga2O3 thermal conductivity to 6.0 W/m K and a 20% increase in the thermal boundary conductance. However, upon further annealing up to 10 h and fully recrystallizing both the Al2O3 interlayer and bonded interface, the thermal boundary conductance dropped by ∼30%. This preliminary result suggests that crystalline heterointerfaces may not necessarily be the most optimal interfacial structure for thermal transport.

<h3>Background</h3> Distal vessel occlusion (DVO) thrombectomy (M3, A2, P2, and beyond) has shown promising outcomes and safety profiles comparable to large vessel occlusion thrombectomy.¹ Simple aspiration is associated with lower rates of symptomatic intracranial hemorrhage than stent-retriever.² Novel, highly trackable bevel tipped .035 aspiration microcatheters (‘Zoom 0.035’) are promising for reperfusion of both de novo and rescue DVO thrombectomy. <h3>Methods</h3> This is a retrospective single-arm, multi-institutional observational study evaluating the efficacy and safety of aspiration thrombectomy for DVO using the Zoom .035 microcatheter. Information regarding patient demographics, presenting/discharge NIHSS, primary/rescue thrombectomy, site of occlusion, TICI score, and intracranial hemorrhage was chart abstracted. Descriptive statistics were used to evaluate the efficacy of thrombectomy both clinically and radiographically. <h3>Results</h3> Fifteen patients (8 male [53.3%]; mean age 65.5±14.0 years) underwent aspiration thrombectomy of DVO using the Zoom .035 microcatheter. The mean NIHSS at presentation was 11±5.3, and the mean ASPECTS was 9.1±0.9. Nine patients (60%) received tPA. Primary occlusion location was M3 in eleven cases (73.3%), V4 VA in one case (6.7%), A2 in one case (6.7%), A3 in one case (6.7%), and P1 in one case (6.7%). Rescue treatment (distal thrombectomy performed following aspiration of a more proximal lesion) occurred in 2/15 cases (13.3%), M3 in one case and P2 in the other. TICI scores were 3 in eight cases (53.3%), 2c in three case (20%), and 2b in four cases (26.7%). There was one postoperative SAH (6.7%) and one ICH (6.7%) that was asymptomatic. Mean discharge NIHSS was 1.9±2.7, with a mean decrease of 7.4±4.5 from presentation (p&lt;0.0001, T-test). Mean length of stay was 4.2±1.6 days. 8/10 patients (80%) had an mRS of 0-2 at 90-day follow-up, with a mean mRS of 1.2±1.8. There was one mortality due to GI bleeding and V-fib arrest.<b>Conclusion</b>: Zoom .035 beveled-tip aspiration microcatheters are highly trackable and associated with improved radiographic and clinical outcomes for the treatment of DVO with a good safety profile. <h3>References</h3> Alawieh AM, Chalhoub RM, Al Kasab S, <i>et al</i>. Multicenter investigation of technical and clinical outcomes after thrombectomy for distal vessel occlusion by frontline technique. <i>J Neurointerv Surg.</i> 2022. Grieb D, Greling B, Schulz K, <i>et al</i>. Endovascular treatment of distal medium vessel occlusions using microcatheter aspiration thrombectomy. <i>Interv Neuroradiol.</i> 2022:15910199221133470. <h3>Disclosures</h3> <b>V. Nguyen:</b> None. <b>J. Dallas:</b> None. <b>J. Sequeiros Chirinos:</b> None. <b>S. Graham:</b> None. <b>J. Burns-Martin:</b> None. <b>N. Goyal:</b> None. <b>K. Khatibi:</b> None.

High Resolution Image Download MS PowerPoint Slide HfO x -based synapses are widely accepted as a viable candidate for both in-memory and neuromorphic computing. Resistance change in oxide-based synapses is caused by the motion of oxygen vacancies. HfO x -based synapses typically demonstrate an abrupt nonlinear resistance change under positive bias application (set), limiting their viability as analog memory. In this work, a thin barrier layer of AlO x or SiO x is added to the bottom electrode/oxide interface to slow the migration of oxygen vacancies. Electrical results show that the resistance change in HfO x /SiO x devices is more controlled than the HfO x devices during the set. While the on/off ratio for the HfO x /SiO x devices is still large (∼10), it is shown to be smaller than that of HfO x /AlO x and HfO x devices. Finite element modeling suggests that the slower oxygen vacancy migration in HfO x /SiO x devices during reset results in a narrower rupture region in the conductive filament. The narrower rupture region causes a lower high resistance state and, thus, a smaller on/off ratio for the HfO x /SiO x devices. Overall, the results show that slowing the motion of oxygen vacancies in the barrier layer devices improves the resistance change during the set but lowers the on/off ratio.

As the demand for computing applications capable of processing large datasets increases, there is a growing need for new in-memory computing technologies. Oxide-based resistive random-access memory (RRAM) devices are promising candidates for such applications because of their industry readiness, endurance, and switching ratio. These analog devices, however, suffer from poor linearity and asymmetry in their analog resistance change. Various reports have found that the temperature in RRAM devices increases locally by more than 1000 K during operation. Therefore, temperature control is of paramount importance for controlling their resistance. In this study, scanning thermal microscopy is used to map the temperature of Au/Ti/HfOx/Au devices at a steady power state and to measure temperature dynamics of the top electrode above the filament location during both resistive switching loops and voltage pulsing. These measurements are used to verify the thermal parameters of a multiphysics finite elements model. The model is then used to understand the impact of thermal conductivities and boundary conductances of constituent materials on resistance change during the first reset pulse in RRAM devices. It is found that the resistance change can be reduced significantly when the temperature in the titanium capping layer is reduced. We find that the greatest temperature reduction and, therefore, the lowest resistance change in the device are afforded by capping layers with increased thermal conductivities. This work links thermal properties to the resistance change in RRAM devices, providing critical insights into engineering devices with improved switching dynamics.

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;This paper presents an experimental method for measuring transmission paths from the exterior to the interior of a passenger vehicle using a reciprocal approach: A production vehicle was placed in a semi-anechoic environment; artificial noise sources were placed at the location of the occupant’s ear(s) inside the vehicle and beamforming arrays with a total of more than 300 microphones were used to observe apparent noise sources on the vehicle exterior resulting from transmission paths. This makes it possible to quickly measure transmission paths over the whole vehicle body.&lt;/div&gt;&lt;div class="htmlview paragraph"&gt;One of the motivations for this work is the monitoring of sealing quality on production vehicles. Artificial seal breaches were introduced on the vehicle and a number of excitation signals were assessed to develop a method to detect and localise leakage noise sources.&lt;/div&gt;&lt;div class="htmlview paragraph"&gt;The investigation and methodology demonstrate the potential for the use of reciprocal beamforming to detect acoustic transmission paths with a view to identifying errors that would impact a vehicle’s wind noise performance, for instance in a manufacturing environment. In addition, it also shows benefits in the use of a similar approach for detecting non-leakage transmission weaknesses, which has applications including the comparison of the isolation performance of various vehicles to external noises.&lt;/div&gt;&lt;/div&gt;

<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -phase gallium oxide ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3) has drawn significant attention due to its large critical electric field strength and the availability of low-cost high-quality melt-grown substrates. Both aspects are advantages over gallium nitride (GaN) and silicon carbide (SiC) based power switching devices. However, because of the poor thermal conductivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3, device-level thermal management is critical to avoid performance degradation and component failure due to overheating. In addition, for high-frequency operation, the low thermal diffusivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3 results in a long thermal time constant, which hinders the use of previously developed thermal solutions for devices based on relatively high thermal conductivity materials (e.g., GaN transistors). This work investigates a double-side diamond-cooled <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3 device architecture and provides guidelines to maximize the device’s thermal performance under both direct current (dc) and high-frequency switching operation. Under high-frequency operation, the use of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3 composite substrate (bottom-side cooling) must be augmented by a diamond passivation overlayer (top-side cooling) because of the low thermal diffusivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -Ga2O3.

Resistive random-access memory (RRAM) devices have been widely studied for neuromorphic, in-memory computing. One of the most studied RRAM structures consists of a titanium capping layer and a HfOx adaptive oxide. Although these devices show promise in improving neuromorphic circuits, high variability, non-linearity, and asymmetric resistance changes limit their usefulness. Many studies have improved linearity by changing materials in or around the device, the circuitry, or the analog bias conditions. However, the impact of prior biasing conditions on the observed analog resistance change is not well understood. Experimental results in this study demonstrate that prior higher reset voltages used after forming cause a greater resistance change during subsequent identical analog pulsing. A multiphysics finite element model suggests that this greater analog resistance change is due to a higher concentration of oxygen ions stored in the titanium capping layer with increasing magnitude of the reset voltage. This work suggests that local ion concentration variations in the titanium capping layer of just tens of atoms cause significant resistance variation during analog operation.